Searched +full:0 +full:xc0002000 (Results 1 – 4 of 4) sorted by relevance
99 reg = <0xf8050000 0x2000100 0xf8040000 0x1000101 0xc0000000 0x2000>;105 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,106 <0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;108 bus-range = <0x00 0xff>;112 interrupt-map-mask = <0 0 0 0x7>;113 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,114 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,115 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,[all …]
19 #size-cells = <0>;21 cpu0: cpu@0 {24 reg = <0x0 0x0>;30 reg = <0x0 0x1>;37 reg = <0x0 0x2>;44 reg = <0x0 0x3>;58 cpu_suspend = <0x84000001>;59 cpu_off = <0x84000002>;60 cpu_on = <0x84000003>;67 reg = <0x0 0xc0001000 0x1000>,[all …]
55 #size-cells = <0>;57 cpu0: cpu@0 {60 reg = <0>;74 reg = <0xf8000000 0x48>;80 psci_version = <0x84000000>;81 cpu_on = <0x84000003>;82 system_reset = <0x84000009>;87 reg = <0xfaf00000 0x58>;92 #clock-cells = <0>;98 #clock-cells = <0>;[all …]
12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */17 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */25 #define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */32 #define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */47 #define MCI_STATUS_MSCOD(m) (((m) >> 16) & 0xffff)63 #define MCI_CONFIG_MCAX 0x165 #define MCI_IPID_MCATYPE 0xFFFF000066 #define MCI_IPID_HWID 0xFFF70 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected76 #define MCACOD 0xefff /* MCA Error Code */[all …]