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/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908-samsung-coreprimevelte.dts25 reg = <0 0x17177000 0 (480 * 800 * 4)>;
34 memory@0 {
36 reg = <0 0 0 0>;
45 reg = <0 0x17000000 0 0x1800000>;
50 reg = <0 0x9000000 0 0x1000000>;
55 reg = <0 0x5000000 0 0x3000000>;
59 reg = <0 0xa000000 0 0x80000>;
63 reg = <0 0x8000000 0 0x100000>;
68 reg = <0 0x8100000 0 0x40000>;
69 record-size = <0x8000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4.dtsi19 #size-cells = <0>;
58 cpu0: cpu@0 {
60 reg = <0x000>;
63 i-cache-size = <0xc000>;
66 d-cache-size = <0x8000>;
74 reg = <0x001>;
77 i-cache-size = <0xc000>;
80 d-cache-size = <0x8000>;
88 reg = <0x002>;
91 i-cache-size = <0xc000>;
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
43 CPU0: cpu@0 {
46 reg = <0x0>;
49 i-cache-size = <0xC000>;
52 d-cache-size = <0x8000>;
62 reg = <0x1>;
65 i-cache-size = <0xC000>;
68 d-cache-size = <0x8000>;
77 reg = <0x100>;
[all …]
/linux/include/linux/mfd/wm8350/
H A Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/linux/arch/powerpc/boot/dts/
H A Dpcm030.dts28 cell-index = <0>;
59 phy0: ethernet-phy@0 {
60 reg = <0>;
67 reg = <0x51>;
71 reg = <0x52>;
78 reg = <0x8000 0x4000>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
85 0xc000 0 0 2 &mpc5200_pic 1 1 3
86 0xc000 0 0 3 &mpc5200_pic 1 2 3
[all …]
H A Ddigsy_mtc.dts19 memory@0 {
20 reg = <0x00000000 0x02000000>; // 32MB
57 phy0: ethernet-phy@0 {
58 reg = <0>;
65 reg = <0x50>;
70 reg = <0x56>;
75 reg = <0x68>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
87 0xc000 0 0 2 &mpc5200_pic 0 0 3
[all …]
H A Dmedia5200.dts28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-pmics.dtsi11 pmm8540a: pmic@0 {
13 reg = <0x0 SPMI_USID>;
15 #size-cells = <0>;
19 reg = <0x6000>, <0x6100>;
21 interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
27 reg = <0xc000>;
29 gpio-ranges = <&pmm8540a_gpios 0 0 10>;
38 reg = <0x4 SPMI_USID>;
40 #size-cells = <0>;
44 reg = <0xb110>;
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap806-quad.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x000>;
21 clocks = <&cpu_clk 0>;
22 i-cache-size = <0xc000>;
25 d-cache-size = <0x8000>;
33 reg = <0x001>;
36 clocks = <&cpu_clk 0>;
37 i-cache-size = <0xc000>;
40 d-cache-size = <0x8000>;
[all …]
H A Darmada-ap807-quad.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x000>;
21 clocks = <&cpu_clk 0>;
22 i-cache-size = <0xc000>;
25 d-cache-size = <0x8000>;
33 reg = <0x001>;
36 clocks = <&cpu_clk 0>;
37 i-cache-size = <0xc000>;
40 d-cache-size = <0x8000>;
[all …]
H A Darmada-ap806-dual.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x000>;
21 clocks = <&cpu_clk 0>;
22 i-cache-size = <0xc000>;
25 d-cache-size = <0x8000>;
33 reg = <0x001>;
36 clocks = <&cpu_clk 0>;
37 i-cache-size = <0xc000>;
40 d-cache-size = <0x8000>;
[all …]
/linux/sound/soc/codecs/
H A Drt1308-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
/linux/arch/csky/kernel/probes/
H A Ddecode-insn.h15 #define is_insn32(insn) ((insn & 0xc000) == 0xc000)
/linux/include/linux/
H A Data.h21 #define ATA_DMA_BOUNDARY 0xffffUL
22 #define ATA_DMA_MASK 0xffffffffULL
37 ATA_ID_CONFIG = 0,
103 ATA_PIO0 = (1 << 0),
113 ATA_SWDMA0 = (1 << 0),
119 ATA_MWDMA0 = (1 << 0),
128 ATA_UDMA0 = (1 << 0),
149 ATA_DMA_CMD = 0,
151 ATA_DMA_START = (1 << 0),
154 ATA_DMA_ACTIVE = (1 << 0),
[all …]
/linux/drivers/media/dvb-frontends/
H A Dau8522_common.c22 } while (0)
33 u8 buf[] = { (reg >> 8) | 0x80, reg & 0xff, data }; in au8522_writereg()
36 .flags = 0, .buf = buf, .len = 3 }; in au8522_writereg()
41 printk("%s: writereg error (reg == 0x%02x, val == 0x%04x, ret == %i)\n", in au8522_writereg()
44 return (ret != 1) ? -1 : 0; in au8522_writereg()
51 u8 b0[] = { (reg >> 8) | 0x40, reg & 0xff }; in au8522_readreg()
52 u8 b1[] = { 0 }; in au8522_readreg()
55 { .addr = state->config.demod_address, .flags = 0, in au8522_readreg()
65 return b1[0]; in au8522_readreg()
80 return 0; in au8522_i2c_gate_ctrl()
[all …]
/linux/include/media/i2c/
H A Dm52790.h14 #define M52790_SW1_IN_MASK 0x0003
15 #define M52790_SW1_IN_TUNER 0x0000
16 #define M52790_SW1_IN_V2 0x0001
17 #define M52790_SW1_IN_V3 0x0002
18 #define M52790_SW1_IN_V4 0x0003
21 #define M52790_SW1_YCMIX 0x0004
26 #define M52790_SW2_IN_MASK 0x0300
27 #define M52790_SW2_IN_TUNER 0x0000
28 #define M52790_SW2_IN_V2 0x0100
29 #define M52790_SW2_IN_V3 0x020
[all...]
/linux/include/linux/mfd/wm831x/
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/linux/include/uapi/linux/
H A Dxilinx-v4l2-controls.h26 #define V4L2_CID_XILINX_OFFSET 0xc000
37 #define V4L2_CID_XILINX_TPG (V4L2_CID_USER_BASE + 0xc000)
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]

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