/freebsd/sys/contrib/device-tree/src/arm64/amazon/ |
H A D | alpine-v3.dtsi | 21 #size-cells = <0>; 23 cpu@0 { 26 reg = <0x0>; 28 d-cache-size = <0x8000>; 31 i-cache-size = <0xc000>; 40 reg = <0x1>; 42 d-cache-size = <0x8000>; 45 i-cache-size = <0xc000>; 54 reg = <0x2>; 56 d-cache-size = <0x8000>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/amd/ |
H A D | amd-seattle-cpus.dtsi | 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 43 CPU0: cpu@0 { 46 reg = <0x0>; 49 i-cache-size = <0xC000>; 52 d-cache-size = <0x8000>; 62 reg = <0x1>; 65 i-cache-size = <0xC000>; 68 d-cache-size = <0x8000>; 77 reg = <0x100>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | pm8450a.dtsi | 10 pm8450a: pmic@0 { 12 reg = <0x0 SPMI_USID>; 14 #size-cells = <0>; 18 reg = <0xc000>; 20 gpio-ranges = <&pm8450a_gpios 0 0 10>; 29 reg = <0x4 SPMI_USID>; 31 #size-cells = <0>; 35 reg = <0xc000>; 37 gpio-ranges = <&pm8450c_gpios 0 0 10>; 46 reg = <0x8 SPMI_USID>; [all …]
|
H A D | sa8540p-pmics.dtsi | 11 pmm8540a: pmic@0 { 13 reg = <0x0 SPMI_USID>; 15 #size-cells = <0>; 19 reg = <0x6000>, <0x6100>; 21 interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; 27 reg = <0xc000>; [all...] |
/freebsd/sys/contrib/device-tree/src/powerpc/ |
H A D | pcm030.dts | 28 cell-index = <0>; 59 phy0: ethernet-phy@0 { 60 reg = <0>; 67 reg = <0x51>; 71 reg = <0x52>; 78 reg = <0x8000 0x4000>; 83 interrupt-map-mask = <0xf800 0 0 7>; 84 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 85 0xc000 0 0 2 &mpc5200_pic 1 1 3 86 0xc000 0 0 3 &mpc5200_pic 1 2 3 [all …]
|
H A D | digsy_mtc.dts | 19 memory@0 { 20 reg = <0x00000000 0x02000000>; // 32MB 57 phy0: ethernet-phy@0 { 58 reg = <0>; 65 reg = <0x50>; 70 reg = <0x56>; 75 reg = <0x68>; 85 interrupt-map-mask = <0xf800 0 0 7>; 86 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 87 0xc000 0 0 2 &mpc5200_pic 0 0 3 [all …]
|
H A D | media5200.dts | 28 PowerPC,5200@0 { 35 memory@0 { 36 reg = <0x00000000 0x08000000>; // 128MB RAM 72 phy0: ethernet-phy@0 { 73 reg = <0>; 78 reg = <0x1000 0x100>; 83 interrupt-map-mask = <0xf800 0 0 7>; 84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 85 0xc000 0 0 2 &media5200_fpga 0 3 86 0xc000 0 0 3 &media5200_fpga 0 4 [all …]
|
H A D | a4m072.dts | 27 ranges = <0 0xf0000000 0x0000c000>; 28 reg = <0xf0000000 0x00000100>; 29 bus-frequency = <0>; /* From boot loader */ 30 system-frequency = <0>; /* From boot loader */ 33 fsl,init-ext-48mhz-en = <0x0>; 34 fsl,init-fd-enable = <0x01>; 35 fsl,init-fd-counters = <0x3333>; 44 reg = <0x2000 0x100>; 45 interrupts = <2 1 0>; 50 reg = <0x2200 0x100>; [all …]
|
H A D | mpc834x_mds.dts | 27 #size-cells = <0>; 29 PowerPC,8349@0 { 31 reg = <0x0>; 36 timebase-frequency = <0>; // from bootloader 37 bus-frequency = <0>; // from bootloader 38 clock-frequency = <0>; // from bootloader 44 reg = <0x00000000 0x10000000>; // 256MB at 0 49 reg = <0xe2400000 0x8000>; 57 ranges = <0x0 0xe0000000 0x00100000>; 58 reg = <0xe0000000 0x00000200>; [all …]
|
H A D | lite5200b.dts | 22 gpios = <&gpt2 0 1>; 25 gpios = <&gpt3 0 1>; 34 memory@0 { 35 reg = <0x00000000 0x10000000>; // 256MB 41 cell-index = <0>; 87 phy0: ethernet-phy@0 { 88 reg = <0>; 95 reg = <0x50>; 101 reg = <0x8000 0x4000>; 106 interrupt-map-mask = <0xf800 0 0 7>; [all …]
|
H A D | pcm032.dts | 23 memory@0 { 24 reg = <0x00000000 0x08000000>; // 128MB 30 cell-index = <0>; 61 phy0: ethernet-phy@0 { 62 reg = <0>; 69 reg = <0x51>; 73 reg = <0x52>; 80 interrupt-map-mask = <0xf800 0 0 7>; 81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 82 0xc000 0 0 2 &mpc5200_pic 1 1 3 [all …]
|
H A D | tqm5200.dts | 20 #size-cells = <0>; 22 PowerPC,5200@0 { 24 reg = <0>; 27 d-cache-size = <0x4000>; // L1, 16K 28 i-cache-size = <0x4000>; // L1, 16K 29 timebase-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader 35 memory@0 { 37 reg = <0x00000000 0x04000000>; // 64MB [all …]
|
H A D | charon.dts | 23 #size-cells = <0>; 25 PowerPC,5200@0 { 27 reg = <0>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 38 memory@0 { 40 reg = <0x00000000 0x08000000>; // 128MB [all …]
|
H A D | pq2fads.dts | 26 #size-cells = <0>; 28 cpu@0 { 30 reg = <0x0>; 35 timebase-frequency = <0>; 36 clock-frequency = <0>; 42 reg = <0x0 0x0>; 50 reg = <0xf0010100 0x60>; 52 ranges = <0x0 0x0 0xff800000 0x800000 53 0x1 0x0 0xf4500000 0x8000 54 0x8 0x0 0xf8200000 0x8000>; [all …]
|
H A D | mpc8272ads.dts | 25 #size-cells = <0>; 27 PowerPC,8272@0 { 29 reg = <0x0>; 34 timebase-frequency = <0>; 35 bus-frequency = <0>; 36 clock-frequency = <0>; 42 reg = <0x0 0x0>; 50 reg = <0xf0010100 0x40>; 52 ranges = <0x0 0x0 0xff800000 0x00800000 53 0x1 0x0 0xf4500000 0x8000 [all …]
|
H A D | lite5200.dts | 20 #size-cells = <0>; 22 PowerPC,5200@0 { 24 reg = <0>; 27 d-cache-size = <0x4000>; // L1, 16K 28 i-cache-size = <0x4000>; // L1, 16K 29 timebase-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader 35 memory@0 { 37 reg = <0x00000000 0x04000000>; // 64MB [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-j784s4.dtsi | 26 #size-cells = <0>; 65 cpu0: cpu@0 { 67 reg = <0x000>; 70 i-cache-size = <0xc000>; 73 d-cache-size = <0x8000>; 81 reg = <0x001>; 84 i-cache-size = <0xc000>; 87 d-cache-size = <0x8000>; 95 reg = <0x002>; 98 i-cache-size = <0xc000>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
H A D | armada-ap806-quad.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0x000>; 24 clocks = <&cpu_clk 0>; 25 i-cache-size = <0xc000>; 28 d-cache-size = <0x8000>; 36 reg = <0x001>; 39 clocks = <&cpu_clk 0>; 40 i-cache-size = <0xc000>; 43 d-cache-size = <0x8000>; [all …]
|
H A D | armada-ap807-quad.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0x000>; 24 clocks = <&cpu_clk 0>; 25 i-cache-size = <0xc000>; 28 d-cache-size = <0x8000>; 36 reg = <0x001>; 39 clocks = <&cpu_clk 0>; 40 i-cache-size = <0xc000>; 43 d-cache-size = <0x8000>; [all …]
|
H A D | armada-ap806-dual.dtsi | 16 #size-cells = <0>; 18 cpu0: cpu@0 { 21 reg = <0x000>; 24 clocks = <&cpu_clk 0>; 25 i-cache-size = <0xc000>; 28 d-cache-size = <0x8000>; 36 reg = <0x001>; 39 clocks = <&cpu_clk 0>; 40 i-cache-size = <0xc000>; 43 d-cache-size = <0x8000>; [all …]
|
/freebsd/contrib/file/magic/Magdir/ |
H A D | xenix | 14 0 string core core file (Xenix) 20 0 byte 0x80 27 >>1 uleshort >0 29 >>>3 ubyte >0 31 >>>>(1.s+3) ubyte >0x6D 33 >>>>>(1.s+3) ubyte <0xF2 8086 relocatable (Microsoft) 50 0 leshort 0xff65 Microsoft x.out 52 >0 byte x archive 66 0 leshort 0x206 67 >0x1c byte&0xc0 =0x40 Microsoft x.out little-endian [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/tesla/ |
H A D | fsd.dtsi | 39 #size-cells = <0>; 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 92 reg = <0x0 0x000>; 96 i-cache-size = <0xc000>; 99 d-cache-size = <0x8000>; 108 reg = <0x0 0x001>; 112 i-cache-size = <0xc000>; 115 d-cache-size = <0x8000>; 124 reg = <0x0 0x002>; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | fsl-lx2160a.dtsi | 12 /memreserve/ 0x80000000 0x00010000; 26 #size-cells = <0>; 29 cpu0: cpu@0 { 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 38 i-cache-size = <0xC000>; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; [all …]
|
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | mpc8548cds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x01000000>; 44 partition@0 { 45 reg = <0x0 0x0b00000>; 50 reg = <0x0b00000 0x0400000>; 55 reg = <0x0f00000 0x060000>; 60 reg = <0x0f60000 0x020000>; 66 reg = <0x0f80000 0x080000>; 72 board-control@1,0 { 74 reg = <0x1 0x0 0x1000>; [all …]
|
/freebsd/sys/dev/mii/ |
H A D | jmphyreg.h | 38 #define JMPHY_SSR 0x11 39 #define JMPHY_SSR_SPEED_1000 0x8000 40 #define JMPHY_SSR_SPEED_100 0x4000 41 #define JMPHY_SSR_SPEED_10 0x0000 42 #define JMPHY_SSR_SPEED_MASK 0xC000 43 #define JMPHY_SSR_DUPLEX 0x2000 44 #define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800 45 #define JMPHY_SSR_LINK_UP 0x0400 46 #define JMPHY_SSR_MDI_XOVER 0x0040 47 #define JMPHY_SSR_INV_POLARITY 0x0002 [all …]
|