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/linux/fs/xfs/scrub/
H A Dcow_repair.c91 * space. Caller must ensure that the physical range is within xc->irec.
95 struct xrep_cow *xc, in xrep_cow_mark_file_range() argument
101 startoff = xc->irec.br_startoff + in xrep_cow_mark_file_range()
102 (startblock - xc->irec.br_startblock); in xrep_cow_mark_file_range()
104 trace_xrep_cow_mark_file_range(xc->sc->ip, startblock, startoff, in xrep_cow_mark_file_range()
107 return xoff_bitmap_set(&xc->bad_fileoffs, startoff, blockcount); in xrep_cow_mark_file_range()
116 struct xrep_cow *xc, in xrep_cow_trim_refcount() argument
124 if (dst->rc_startblock < xc->irec_startbno) { in xrep_cow_trim_refcount()
125 adj = xc->irec_startbno - dst->rc_startblock; in xrep_cow_trim_refcount()
131 xc->irec_startbno + xc->irec.br_blockcount) { in xrep_cow_trim_refcount()
[all …]
/linux/drivers/ata/pata_parport/
H A Dfit3.c23 #define j44(a, b) (((a >> 3) & 0x0f) | ((b << 1) & 0xf0))
26 #define r7() (in_p(7) & 0xff)
29 * cont = 0 - access the IDE register file
38 case 0: in fit3_write_regr()
40 w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
41 w0(val); w2(0xd); in fit3_write_regr()
42 w0(0); w2(0xc); in fit3_write_regr()
45 w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
46 w4(val); w4(0); in fit3_write_regr()
47 w2(0xc); in fit3_write_regr()
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c39 static void xive_vm_ack_pending(struct kvmppc_xive_vcpu *xc) in xive_vm_ack_pending() argument
63 cppr = ack & 0xff; in xive_vm_ack_pending()
65 xc->pending |= 1 << cppr; in xive_vm_ack_pending()
68 if (cppr >= xc->hw_cppr) in xive_vm_ack_pending()
70 smp_processor_id(), cppr, xc->hw_cppr); in xive_vm_ack_pending()
74 * xc->cppr, this will be done as we scan for interrupts in xive_vm_ack_pending()
77 xc->hw_cppr = cppr; in xive_vm_ack_pending()
99 __raw_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in xive_vm_source_eoi()
123 __raw_writeq(0, __x_trig_page(xd)); in xive_vm_source_eoi()
133 static u32 xive_vm_scan_interrupts(struct kvmppc_xive_vcpu *xc, in xive_vm_scan_interrupts() argument
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_13_0_2_sh_mask.h30 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
31 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
32 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
33 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
34 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
35 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
36 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
37 …N_CUR_TMP__MCM_EN__SHIFT 0x14
38 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
39 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
H A Dthm_9_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
H A Dthm_10_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
/linux/arch/powerpc/sysdev/xive/
H A Dcommon.c43 #define DBG_VERBOSE(fmt...) do { } while(0)
99 * or 0 if there is no new entry.
108 return 0; in xive_read_eq()
113 return 0; in xive_read_eq()
121 if (q->idx == 0) in xive_read_eq()
125 return cur & 0x7fffffff; in xive_read_eq()
135 * (0xff if none) and return what was found (0 if none).
151 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) in xive_scan_interrupts() argument
153 u32 irq = 0; in xive_scan_interrupts()
154 u8 prio = 0; in xive_scan_interrupts()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_7_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_8_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_9_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_9_1_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_1_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_0_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_4_1_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h27 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
28 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
29 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
30 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
31 …_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
32 …_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
33 …_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
34 …_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
36 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
37 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
[all …]
H A Ddcn_3_0_2_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_2_0_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_3_0_0_sh_mask.h8 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
9 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
10 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
11 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
13 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
14 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
15 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
16 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
18 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
19 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vpe/
H A Dvpe_6_1_0_sh_mask.h29 …EC_START__START__SHIFT 0x0
30 …__START_MASK 0xFFFFFFFFL
32 …CODE_ADDR__VALUE__SHIFT 0x0
33 …CODE_ADDR__THID__SHIFT 0xf
34 …R__VALUE_MASK 0x00001FFFL
35 …R__THID_MASK 0x00008000L
37 …CODE_DATA__VALUE__SHIFT 0x0
38 …A__VALUE_MASK 0xFFFFFFFFL
40 …32_CNTL__HALT__SHIFT 0x0
41 …32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]

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