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/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dfsl,bman.yaml34 registers which are located at offsets 0xbf8 and 0xbfc
78 reg = <0x31a000 0x1000>;
80 fsl,liodn = <0x17>;
H A Dfsl,qman.yaml35 registers which are located at offsets 0xbf8 and 0xbfc
87 reg = <0x318000 0x1000>;
89 fsl,liodn = <0x16>;
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_common.h24 #define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
29 #define CN10K_MBOX 0
41 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
42 #define MBOX_MSG_RX_INLINE_IPSEC_LF_CFG 0xBFE
43 #define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
44 #define MBOX_MSG_GET_CAPS 0xBFD
45 #define MBOX_MSG_GET_KVF_LIMITS 0xBFC
159 ((pdev->revision & 0xFF) == 4 || in is_dev_cn10ka_ax()
160 (pdev->revision & 0xFF) == 0x50 || in is_dev_cn10ka_ax()
161 (pdev->revision & 0xFF) == 0x51); in is_dev_cn10ka_ax()
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/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-regmap.c60 case MCP251XFD_REG_FLTCON(0): in mcp251xfd_update_bits_read_reg()
76 WARN(1, "Status of reg 0x%04x unknown.\n", reg); in mcp251xfd_update_bits_read_reg()
90 __le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32; in mcp251xfd_regmap_nocrc_update_bits()
98 mask == 0) in mcp251xfd_regmap_nocrc_update_bits()
110 spi_message_add_tail(&xfer[0], &msg); in mcp251xfd_regmap_nocrc_update_bits()
113 xfer[0].tx_buf = buf_tx; in mcp251xfd_regmap_nocrc_update_bits()
114 xfer[0].len = sizeof(buf_tx->cmd); in mcp251xfd_regmap_nocrc_update_bits()
120 xfer[0].tx_buf = buf_tx; in mcp251xfd_regmap_nocrc_update_bits()
121 xfer[0].rx_buf = buf_rx; in mcp251xfd_regmap_nocrc_update_bits()
122 xfer[0].len = sizeof(buf_tx->cmd) + len; in mcp251xfd_regmap_nocrc_update_bits()
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun50i-a100.c31 #define SUN50I_A100_PLL_PERIPH1_PATTERN0 0xd1303333
41 * testing", so it's not modelled and then force to 0.
43 #define SUN50I_A100_PLL_CPUX_REG 0x000
49 .reg = 0x000,
57 #define SUN50I_A100_PLL_DDR0_REG 0x010
63 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
65 .reg = 0x010,
73 #define SUN50I_A100_PLL_PERIPH0_REG 0x020
79 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
82 .reg = 0x020,
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H A Dccu-sun20i-d1.c34 * in the user manual. So it's not modelled and forced to 0.
36 #define SUN20I_D1_PLL_CPUX_REG 0x000
42 .reg = 0x000,
50 #define SUN20I_D1_PLL_DDR0_REG 0x010
56 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
58 .reg = 0x010,
65 #define SUN20I_D1_PLL_PERIPH0_REG 0x020
72 .reg = 0x020,
83 pll_periph0_4x_hws, 0x020, 16, 3, 0);
85 pll_periph0_4x_hws, 0x020, 20, 3, 0);
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H A Dccu-sun55i-a523.c45 #define SUN55I_A523_PLL_DDR0_REG 0x010
51 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
53 .reg = 0x010,
66 #define SUN55I_A523_PLL_PERIPH0_REG 0x020
73 .reg = 0x020,
94 pll_periph0_4x_hws, 0x020, 16, 3, 0);
99 pll_periph0_4x_hws, 0x020, 20, 3, 0);
101 pll_periph0_4x_hws, 0x020, 2, 3, 0);
106 pll_periph0_2x_hws, 2, 1, 0);
108 pll_periph0_2x_hws, 3, 1, 0);
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.h13 #define CORE_ID 0x0
14 #define VER_NUMBER 0x4
15 #define VER_TYPE 0x8
16 #define CONFIG_REG 0xc
19 #define CORE_TIMESTAMP_HHMM 0x14
20 #define CORE_TIMESTAMP_MMDD 0x18
21 #define CORE_TIMESTAMP_YYYY 0x1c
23 #define GLOBAL_SWRESET_REQUEST 0x40
26 #define GLOBAL_SWDISABLE 0x44
30 #define RESET_MANAGER_CONFIG0 0x48
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