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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dfsl,bman.yaml34 registers which are located at offsets 0xbf8 and 0xbfc
78 reg = <0x31a000 0x1000>;
80 fsl,liodn = <0x17>;
H A Dfsl,qman.yaml35 registers which are located at offsets 0xbf8 and 0xbfc
87 reg = <0x318000 0x1000>;
89 fsl,liodn = <0x16>;
H A Dbman.txt32 are located at offsets 0xbf8 and 0xbfc
106 size = <0 0x1000000>;
107 alignment = <0 0x1000000>;
126 reg = <0x31a000 0x1000>;
128 fsl,liodn = <0x17>;
135 fsl,bman = <&bman, 0>;
H A Dqman.txt34 are located at offsets 0xbf8 and 0xbfc
133 size = <0 0x400000>;
134 alignment = <0 0x400000>;
139 size = <0 0x2000000>;
140 alignment = <0 0x2000000>;
159 reg = <0xc00 0x4>;
175 reg = <0x318000 0x1000>;
177 fsl,liodn = <0x16>;
185 fsl,qman = <&qman, 0>;
/freebsd/sys/dev/tsec/
H A Dif_tsecreg.h29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */
30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */
36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */
37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */
38 #define TSEC_REG_PTV 0x028 /* Pause time value register */
39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */
40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c56 CCU_RESET(RST_MBUS, 0x540, 30)
57 CCU_RESET(RST_BUS_DE, 0x60C, 16)
58 CCU_RESET(RST_BUS_DI, 0x62C, 16)
59 CCU_RESET(RST_BUS_G2D, 0x63C, 16)
60 CCU_RESET(RST_BUS_CE, 0x68C, 16)
61 CCU_RESET(RST_BUS_VE, 0x69C, 16)
62 CCU_RESET(RST_BUS_DMA, 0x70C, 16)
63 CCU_RESET(RST_BUS_MSGBOX0, 0x71C, 16)
64 CCU_RESET(RST_BUS_MSGBOX1, 0x71C, 17)
65 CCU_RESET(RST_BUS_MSGBOX2, 0x71C, 18)
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/freebsd/sys/dev/mpi3mr/mpi/
H A Dmpi30_tool.h53 U16 HostTag; /* 0x00 */
54 U8 IOCUseOnly02; /* 0x02 */
55 U8 Function; /* 0x03 */
56 U16 IOCUseOnly04; /* 0x04 */
57 U8 IOCUseOnly06; /* 0x06 */
58 U8 MsgFlags; /* 0x07 */
59 U16 ChangeCount; /* 0x08 */
60 U8 Tool; /* 0x0A */
61 U8 Reserved0B; /* 0x0B */
62 U32 Area; /* 0x0C */
[all …]
/freebsd/sys/dev/cxgbe/common/
H A Dt4_regs.h36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
63 #define PF_STRIDE 0x400
[all …]