Searched +full:0 +full:xb3000000 (Results 1 – 5 of 5) sorted by relevance
18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)[all …]
39 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); in spear13xx_l2x0_init()45 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); in spear13xx_l2x0_init()46 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); in spear13xx_l2x0_init()47 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); in spear13xx_l2x0_init()53 * 0xB3000000 0xF900000054 * 0xE0000000 0xFD00000055 * 0xEC000000 0xFC00000056 * 0xED000000 0xFB000000
15 ranges = <0x40000000 0x40000000 0x8000000016 0xd0000000 0xd0000000 0x30000000>;20 reg = <0xb3000000 0x1000>;26 reg = <0x90000000 0x1000>;36 reg = <0x4c000000 0x1000 /* FSMC Register */37 0x50000000 0x0010 /* NAND Base DATA */38 0x50020000 0x0010 /* NAND Base ADDR */39 0x50010000 0x0010>; /* NAND Base CMD */46 reg = <0x70000000 0x100>;54 reg = <0xb3000000 0x1000>;[all …]
15 #size-cells = <0>;17 cpu@0 {20 reg = <0>;36 reg = < 0xec801000 0x1000 >,37 < 0xec800100 0x0100 >;42 interrupts = <0 6 0x04>,43 <0 7 0x04>;48 reg = <0xed000000 0x1000>;56 reg = <0 0x40000000>;79 ranges = <0x50000000 0x50000000 0x10000000[all …]
63 reg = <0xb3000000 0x1000>;