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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt41 SDHC System Operation Control Register Bit[7:0].
62 Valid range = [0:0x1F].
63 ZNR is set as 0xF by default if this property is not provided.
68 Valid range = [0:0x1F].
69 ZPR is set as 0xF by default if this property is not provided.
75 Set as 0x4 by default if this property is not provided.
93 be set as 0x9 in driver.
110 reg = <0xaa0000 0x1000>;
128 reg = <0xab0000 0x1000>;
142 reg = <0xaa0000 0x1000>,
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H A Dsdhci-of-dwcmshc.txt16 reg = <0xaa0000 0x1000>;
H A Dmarvell,xenon-sdhci.yaml66 minimum: 0
70 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
91 minimum: 0
92 maximum: 0x1f
93 default: 0xf
100 minimum: 0
101 maximum: 0x1f
102 default: 0xf
111 default: 0x4
133 default: 0x
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/freebsd/lib/msun/ld128/
H A Ds_logl.c55 * rest of p(d). In the worst case when k = 0 and log(X_i) is 0, the final
70 * in beginning with the Taylor coefficients 0 + 1*d, which tends to happen
98 P3 = 3.33333333333333333333333333333233795e-1L, /* 0x15555555555555555555555554d42.0p-114L */
99 P4 = -2.49999999999999999999999999941139296e-1L, /* -0x1ffffffffffffffffffffffdab14e.0p-115L */
100 P5 = 2.00000000000000000000000085468039943e-1L, /* 0x19999999999999999999a6d3567f4.0p-115L */
101 P6 = -1.66666666666666666666696142372698408e-1L, /* -0x15555555555555555567267a58e1
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/freebsd/lib/msun/ld80/
H A Ds_logl.c55 * rest of p(d). In the worst case when k = 0 and log(X_i) is 0, the final
70 * in beginning with the Taylor coefficients 0 + 1*d, which tends to happen
103 P3 = 3.3333333333333359e-1, /* 0x1555555555555a.0p-54 */
104 P4 = -2.5000000000004424e-1, /* -0x1000000000031d.0p-54 */
105 P5 = 1.9999999992970016e-1, /* 0x1999999972f3c7.0p-55 */
106 P6 = -1.6666666072191585e-1, /* -0x15555548912c0
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