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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-tqma64xxl.dtsi19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
63 pinctrl-0 = <&main_i2c0_pins>;
70 reg = <0x4a>;
76 reg = <0x50>;
85 reg = <0x51>;
91 reg = <0x54>;
[all …]
H A Dk3-am64-phycore-som.dtsi29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
39 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
40 alignment = <0x1000>;
46 reg = <0x00 0xa0000000 0x00 0x100000>;
52 reg = <0x00 0xa0100000 0x00 0xf00000>;
60 pinctrl-0 = <&leds_pins_default>;
62 led-0 {
84 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
85 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
86 AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
[all …]
H A Dk3-am68-phycore-som.dtsi28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
29 <0x00000008 0x80000000 0x00000000 0x80000000>;
42 size = <0x00 0x20000000>;
47 reg = <0x00 0x9e800000 0x00 0x01800000>;
48 alignment = <0x1000>;
54 reg = <0x00 0xa0000000 0x00 0x100000>;
60 reg = <0x00 0xa0100000 0x00 0xf00000>;
70 pinctrl-0 = <&vdd_sd_dv_pins_default>;
75 states = <3300000 0x0>,
76 <1800000 0x1>;
[all …]
H A Dk3-am67a-beagley-ai.dts32 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
33 <0x00000008 0x80000000 0x00000000 0x80000000>;
44 reg = <0x00 0x9e780000 0x00 0x80000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>;
55 reg = <0x00 0xa0000000 0x00 0x100000>;
61 reg = <0x00 0xa0100000 0x00 0xf00000>;
90 pinctrl-0 = <&vdd_3v3_sd_pins_default>;
103 pinctrl-0 = <&vdd_sd_dv_pins_default>;
109 states = <1800000 0x0>,
110 <3300000 0x1>;
[all …]
H A Dk3-am642-sk.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
67 vusb_main: regulator-0 {
110 pinctrl-0 = <&main_com8_ls_en_pins_default>;
122 pinctrl-0 = <&main_wlan_en_pins_default>;
131 led-0 {
135 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
[all …]
H A Dk3-j721e-beagleboneai64.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
41 <0x00000008 0x80000000 0x00000000 0x80000000>;
50 reg = <0x00 0x9e800000 0x00 0x01800000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
70 pinctrl-0 = <&sw_pwr_pins_default>;
75 gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
88 pinctrl-0 = <&led_pins_default>;
90 led-0 {
121 evm_12v0: regulator-0 {
[all …]
H A Dk3-am642-evm.dts42 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
51 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
52 alignment = <0x1000>;
58 reg = <0x00 0xa0000000 0x00 0x100000>;
64 reg = <0x00 0xa0100000 0x00 0xf00000>;
69 evm_12v0: regulator-0 {
131 pinctrl-0 = <&ddr_vtt_pins_default>;
144 led-0 {
155 #mux-control-cells = <0>;
165 #size-cells = <0>;
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]