Home
last modified time | relevance | path

Searched +full:0 +full:xa000000 (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml136 enum: [0, 1]
303 reg = <0x18800000 0x800000>;
320 iommus = <&anoc2_smmu 0x1900>,
321 <&anoc2_smmu 0x1901>;
330 iommus = <&apps_smmu 0x1c02 0x1>;
340 reg = <0xa000000 0x200000>;
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
27 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0>;
110 reg = <0x100>;
115 reg = <0x101>;
120 reg = <0x102>;
125 reg = <0x103>;
130 reg = <0x200>;
135 reg = <0x201>;
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
225 return 0; in goya_coresight_timeout()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmBIF_MM_INDACCESS_CNTL 0x1500
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl692.c36 int ret = 0; in mxl692_i2c_write()
39 .flags = 0, in mxl692_i2c_write()
53 int ret = 0; in mxl692_i2c_read()
72 for (i = 0; i < (size & ~3); i += 4) { in convert_endian()
73 d[i + 0] ^= d[i + 3]; in convert_endian()
74 d[i + 3] ^= d[i + 0]; in convert_endian()
75 d[i + 0] ^= d[i + 3]; in convert_endian()
83 case 0: in convert_endian()
88 d[i + 0] ^= d[i + 1]; in convert_endian()
89 d[i + 1] ^= d[i + 0]; in convert_endian()
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra264.dtsi23 reg = <0x0 0x86070000 0x0 0x2000>;
29 bus@0 {
35 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
39 reg = <0x0 0x00100000 0x0 0x0f000>,
40 <0x0 0x0c140000 0x0 0x10000>;
45 reg = <0x0 0x08000000 0x0 0x140000>;
64 ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>;
68 reg = <0x0 0x9440000 0x0 0xb0000>;
70 interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
[all …]