Home
last modified time | relevance | path

Searched +full:0 +full:xa00 (Results 1 – 25 of 177) sorted by relevance

12345678

/linux/drivers/clk/rockchip/
H A Dclk.h30 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
31 #define BOOST_CLK_CON 0x0008
32 #define BOOST_BOOST_CON 0x000c
33 #define BOOST_SWITCH_CNT 0x0010
34 #define BOOST_HIGH_PERF_CNT0 0x0014
35 #define BOOST_HIGH_PERF_CNT1 0x0018
36 #define BOOST_STATIS_THRESHOLD 0x001c
37 #define BOOST_SHORT_SWITCH_CNT 0x0020
38 #define BOOST_SWITCH_THRESHOLD 0x0024
39 #define BOOST_FSM_STATUS 0x0028
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8167.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
H A Dpinctrl-mt8516.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
27 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
28 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
34 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
50 /* 3. Page8(0x800) */
52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
55 #define rFPGA0_XA_HSSIParameter2 0x824
56 #define rFPGA0_XB_HSSIParameter1 0x828
57 #define rFPGA0_XB_HSSIParameter2 0x82c
58 #define rTxAGC_B_Rate18_06 0x830
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-pmics.dtsi23 hysteresis = <0>;
29 hysteresis = <0>;
43 hysteresis = <0>;
49 hysteresis = <0>;
63 hysteresis = <0>;
69 hysteresis = <0>;
83 hysteresis = <0>;
89 hysteresis = <0>;
98 pmk8280: pmic@0 {
100 reg = <0x0 SPMI_USID>;
[all …]
H A Dpm8450.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
37 reg = <0x7 SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pm8450_gpios 0 0 4>;
H A Dpm7325.dtsi12 reg = <0x1 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pm7325_gpios 0 0 10>;
44 hysteresis = <0>;
50 hysteresis = <0>;
H A Dpmr735d_b.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
37 reg = <0xb SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pmr735d_l_gpios 0 0 2>;
H A Dpmr735d_a.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
37 reg = <0xa SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pmr735d_k_gpios 0 0 2>;
H A Dpmr735b.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x5 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pmr735b_gpios 0 0 4>;
H A Dpm8350.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x1 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350_gpios 0 0 10>;
H A Dpm8350b.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
36 reg = <0x3 SPMI_USID>;
38 #size-cells = <0>;
42 reg = <0xa00>;
43 interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
44 #thermal-sensor-cells = <0>;
49 reg = <0x8800>;
51 gpio-ranges = <&pm8350b_gpios 0 0 8>;
H A Dpmr735a.dtsi12 reg = <0x4 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmr735a_gpios 0 0 4>;
45 hysteresis = <0>;
51 hysteresis = <0>;
H A Dpm8550ve.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <PMK8550VE_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pm8550ve_gpios 0 0 8>;
H A Dpm8550b.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
37 reg = <0x7 SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pm8550b_gpios 0 0 12>;
60 reg = <0xfd00>;
[all …]
H A Dpmx75.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
31 hysteresis = <0>;
44 #size-cells = <0>;
48 reg = <0xa00>;
49 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
50 #thermal-sensor-cells = <0>;
55 reg = <0x8800>;
57 gpio-ranges = <&pmx75_gpios 0 0 16>;
H A Dpm7550ba.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
31 hysteresis = <0>;
44 #size-cells = <0>;
48 reg = <0xa00>;
49 interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
50 #thermal-sensor-cells = <0>;
55 reg = <0x8800>;
57 gpio-ranges = <&pm7550ba_gpios 0 0 8>;
65 reg = <0xfd00>;
[all …]
H A Dpm8350c.dtsi12 reg = <0x2 SPMI_USID>;
14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pm8350c_gpios 0 0 9>;
35 reg = <0xee00>;
57 hysteresis = <0>;
63 hysteresis = <0>;
H A Dpm8550.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
37 reg = <0x1 SPMI_USID>;
39 #size-cells = <0>;
43 reg = <0xa00>;
44 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
45 #thermal-sensor-cells = <0>;
50 reg = <0x8800>;
52 gpio-ranges = <&pm8550_gpios 0 0 12>;
60 reg = <0xee00>;
/linux/drivers/gpio/
H A Dgpio-loongson-64bit.c60 u8 bval = input ? 1 : 0; in loongson_commit_direction()
67 u8 bval = high ? 1 : 0; in loongson_commit_level()
81 return 0; in loongson_gpio_direction_input()
91 loongson_commit_direction(lgpio, pin, 0); in loongson_gpio_direction_output()
94 return 0; in loongson_gpio_direction_output()
130 return 0; in loongson_gpio_set()
157 writeb(0x1, lgpio->reg_base + lgpio->chip_data->intclr_offset + hwirq); in loongson_gpio_irq_ack()
166 writeb(0x0, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); in loongson_gpio_irq_mask()
175 writeb(0x1, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq); in loongson_gpio_irq_unmask()
183 u8 pol = 0, edge = 0, dual = 0; in loongson_gpio_irq_set_type()
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dpmx65.dtsi14 #size-cells = <0>;
18 reg = <0xa00>;
19 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
20 #thermal-sensor-cells = <0>;
25 reg = <0x8800>;
27 gpio-ranges = <&pmx65_gpios 0 0 16>;
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom,spmi-temp-alarm.yaml39 const: 0
54 #size-cells = <0>;
58 reg = <0xa00>;
59 interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
60 #thermal-sensor-cells = <0>;
67 polling-delay = <0>;
73 hysteresis = <0>;
79 hysteresis = <0>;
/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]

12345678