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Searched +full:0 +full:xffffffff (Results 1 – 25 of 1042) sorted by relevance

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/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define MC_CG_SEQ_DRAMCONF_S0 0x05
44 #define MC_CG_SEQ_DRAMCONF_S1 0x06
45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
46 #define MC_CG_SEQ_YCLK_RESUME 0x0a
48 #define SMC_RAM_END 0x8000
58 0x000008f8, 0x00000010, 0xffffffff,
[all …]
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
121 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dtpc0_cfg_masks.h23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
H A Ddma_ch_0_masks.h23 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT 0
24 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK 0x3FF
26 #define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK 0xFFF0000
29 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT 0
30 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK 0x3FF
33 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT 0
34 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
37 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT 0
38 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
41 #define DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT 0
[all …]
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_cfg_masks.h23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_11_0_cdr_table.h36 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0…
37 0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x0…
38 0x0f0f0f0f, 0xf0f00f0f, 0x0f0ff0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf…
39 0xf0f00f0f, 0x0f0ff0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0…
46 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0xf…
47 0xffffffff, 0x0000ffff, 0x00000000, 0xffffffff, 0x00000000, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xf…
48 0xffffffff, 0x0000ffff, 0xffff0000, 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x0000ffff, 0x0…
49 0x0000ffff, 0xffff0000, 0xffff0000, 0x00000000, 0xffff0000, 0x00000000, 0xffffffff, 0x00000000, 0xf…
56 …0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x…
57 …0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x…
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
H A Dmxgpu_vi.c49 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
50 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
51 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
54 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
55 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
56 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
57 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
58 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
H A Dcik.c82 .max_level = 0,
143 return 0; in cik_query_video_codecs()
205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
245 0xc200, 0xe0ffffff, 0xe0000000
250 0x31dc, 0xffffffff, 0x00000800,
251 0x31dd, 0xffffffff, 0x00000800,
252 0x31e6, 0xffffffff, 0x00007fbf,
253 0x31e7, 0xffffffff, 0x00007faf
258 0xcd5, 0x00000333, 0x00000333,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
H A Dsmu_7_0_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_default.h26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
H A Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]

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