/freebsd/contrib/netbsd-tests/lib/libc/gen/ |
H A D | t_floatunditf.c | 38 { 0xffffffffffffffffULL, 0xf.fffffffffffffffp+60L }, 39 { 0xfffffffffffffffeULL, 0xf.ffffffffffffffep+60L }, 40 { 0xfffffffffffffffdULL, 0xf.ffffffffffffffdp+60L }, 41 { 0xfffffffffffffffcULL, 0xf.ffffffffffffffcp+60L }, 42 { 0x7fffffffffffffffULL, 0xf.ffffffffffffffep+59L }, 43 { 0x3fffffffffffffffULL, 0xf.ffffffffffffffcp+58L }, 44 { 0x1fffffffffffffffULL, 0xf.ffffffffffffff8p+57L }, 45 { 0xfffffffffffffffULL, 0xf.ffffffffffffffp+56L }, 46 { 0x7ffffffffffffffULL, 0xf.fffffffffffffep+55L }, 47 { 0x3ffffffffffffffULL, 0xf.fffffffffffffcp+54L }, [all …]
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | cyrus_p5020.dts | 30 size = <0 0x1000000>; 31 alignment = <0 0x1000000>; 34 size = <0 0x400000>; 35 alignment = <0 0x400000>; 38 size = <0 0x2000000>; 39 alignment = <0 0x2000000>; 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 48 ranges = <0x0 0xf 0xf4000000 0x200000>; 52 ranges = <0x0 0xf 0xf4200000 0x200000>; 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | mpc8572ds_36b.dts | 19 reg = <0xf 0xffe05000 0 0x1000>; 21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 22 0x1 0x0 0xf 0xe0000000 0x08000000 23 0x2 0x0 0xf 0xffa00000 0x00040000 24 0x3 0x0 0xf 0xffdf0000 0x00008000 25 0x4 0x0 0xf 0xffa40000 0x00040000 26 0x5 0x0 0xf 0xffa80000 0x00040000 27 0x6 0x0 0xf 0xffac0000 0x00040000>; 31 ranges = <0x0 0xf 0xffe00000 0x100000>; 35 reg = <0xf 0xffe08000 0 0x1000>; [all …]
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H A D | kmcent2.dts | 27 size = <0 0x1000000>; 28 alignment = <0 0x1000000>; 31 size = <0 0x400000>; 32 alignment = <0 0x400000>; 35 size = <0 0x2000000>; 36 alignment = <0 0x2000000>; 41 reg = <0xf 0xfe124000 0 0x2000>; 42 ranges = <0 0 0xf 0xe8000000 0x04000000 43 1 0 0xf 0xfa000000 0x00010000 44 2 0 0xf 0xfb000000 0x00010000 [all …]
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H A D | mpc8536ds_36b.dts | 17 #size-cells = <0>; 19 PowerPC,8536@0 { 21 reg = <0>; 28 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0xf 0xffe05000 0 0x1000>; 34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 35 0x2 0x0 0xf 0xffa00000 0x00040000 36 0x3 0x0 0xf 0xffdf0000 0x00008000>; 40 ranges = <0x0 0xf 0xffe00000 0x100000>; 44 reg = <0xf 0xffe08000 0 0x1000>; [all …]
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H A D | t104xd4rdb.dtsi | 42 size = <0 0x1000000>; 43 alignment = <0 0x1000000>; 46 size = <0 0x400000>; 47 alignment = <0 0x400000>; 50 size = <0 0x2000000>; 51 alignment = <0 0x2000000>; 56 reg = <0xf 0xfe124000 0 0x2000>; 57 ranges = <0 0 0xf 0xe8000000 0x08000000 58 2 0 0xf 0xff800000 0x00010000 59 3 0 0xf 0xffdf0000 0x00008000>; [all …]
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H A D | t104xrdb.dtsi | 48 size = <0 0x1000000>; 49 alignment = <0 0x1000000>; 52 size = <0 0x400000>; 53 alignment = <0 0x400000>; 56 size = <0 0x2000000>; 57 alignment = <0 0x2000000>; 62 reg = <0xf 0xfe124000 0 0x2000>; 63 ranges = <0 0 0xf 0xe8000000 0x08000000 64 2 0 0xf 0xff800000 0x00010000 65 3 0 0xf 0xffdf0000 0x00008000>; [all …]
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H A D | t208xrdb.dtsi | 48 size = <0 0x1000000>; 49 alignment = <0 0x1000000>; 52 size = <0 0x400000>; 53 alignment = <0 0x400000>; 56 size = <0 0x2000000>; 57 alignment = <0 0x2000000>; 62 reg = <0xf 0xfe124000 0 0x2000>; 63 ranges = <0 0 0xf 0xe8000000 0x08000000 64 2 0 0xf 0xff800000 0x00010000 65 3 0 0xf 0xffdf0000 0x00008000>; [all …]
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H A D | mpc8548cds_36b.dts | 16 reg = <0 0 0x0 0x8000000>; // 128M at 0x0 20 reg = <0xf 0xe0005000 0 0x1000>; 22 ranges = <0x0 0x0 0xf 0xff000000 0x01000000 23 0x1 0x0 0xf 0xf8004000 0x00001000>; 28 ranges = <0 0xf 0xe0000000 0x100000>; 32 reg = <0xf 0xe0008000 0 0x1000>; 33 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000 34 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>; 39 reg = <0xf 0xe0009000 0 0x1000>; 40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 [all …]
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H A D | p1022ds_36b.dts | 45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 46 0x1 0x0 0xf 0xe0000000 0x08000000 47 0x2 0x0 0xf 0xff800000 0x00040000 48 0x3 0x0 0xf 0xffdf0000 0x00008000>; 49 reg = <0xf 0xffe05000 0 0x1000>; 53 ranges = <0x0 0xf 0xffe00000 0x100000>; 57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 59 reg = <0xf 0xffe09000 0 0x1000>; 60 pcie@0 { [all …]
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H A D | kmcoge4.dts | 30 size = <0 0x1000000>; 31 alignment = <0 0x1000000>; 34 size = <0 0x400000>; 35 alignment = <0 0x400000>; 38 size = <0 0x2000000>; 39 alignment = <0 0x2000000>; 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 48 ranges = <0x0 0xf 0xf4000000 0x200000>; 52 ranges = <0x0 0xf 0xf4200000 0x200000>; 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p1020rdb_36b.dts | 18 reg = <0xf 0xffe05000 0 0x1000>; 21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000 22 0x1 0x0 0xf 0xffa00000 0x00040000 23 0x2 0x0 0xf 0xffb00000 0x00020000>; 27 ranges = <0x0 0xf 0xffe00000 0x100000>; 31 reg = <0xf 0xffe09000 0 0x1000>; 32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 34 pcie@0 { 35 ranges = <0x2000000 0x0 0xc0000000 [all …]
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H A D | p1021rdb-pc_36b.dts | 45 reg = <0xf 0xffe05000 0 0x1000>; 48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000 49 0x1 0x0 0xf 0xff800000 0x00040000 50 0x2 0x0 0xf 0xffb00000 0x00020000>; 54 ranges = <0x0 0xf 0xffe00000 0x100000>; 58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 60 reg = <0xf 0xffe09000 0 0x1000>; 61 pcie@0 { 62 ranges = <0x2000000 0x0 0xa0000000 [all …]
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H A D | p2020rdb-pc_36b.dts | 46 reg = <0xf 0xffe05000 0 0x1000>; 49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000 50 0x1 0x0 0xf 0xff800000 0x00040000 51 0x2 0x0 0xf 0xffb00000 0x00020000 52 0x3 0x0 0xf 0xffa00000 0x00020000>; 56 ranges = <0x0 0xf 0xffe00000 0x100000>; 60 reg = <0xf 0xffe08000 0 0x1000>; 65 reg = <0xf 0xffe09000 0 0x1000>; 66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; [all …]
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H A D | t208xqds.dtsi | 48 size = <0 0x1000000>; 49 alignment = <0 0x1000000>; 52 size = <0 0x400000>; 53 alignment = <0 0x400000>; 56 size = <0 0x2000000>; 57 alignment = <0 0x2000000>; 62 reg = <0xf 0xfe124000 0 0x2000>; 63 ranges = <0 0 0xf 0xe8000000 0x08000000 64 2 0 0xf 0xff800000 0x00010000 65 3 0 0xf 0xffdf0000 0x00008000>; [all …]
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H A D | t4240rdb.dts | 56 reg = <0xf 0xfe124000 0 0x2000>; 57 ranges = <0 0 0xf 0xe8000000 0x08000000 58 2 0 0xf 0xff800000 0x00010000 59 3 0 0xf 0xffdf0000 0x00008000>; 61 nor@0,0 { 65 reg = <0x0 0x0 0x8000000>; 71 nand@2,0 { 75 reg = <0x2 0x0 0x10000>; 89 size = <0 0x1000000>; 90 alignment = <0 0x1000000>; [all …]
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H A D | t1023rdb.dts | 50 size = <0 0x1000000>; 51 alignment = <0 0x1000000>; 55 size = <0 0x400000>; 56 alignment = <0 0x400000>; 60 size = <0 0x2000000>; 61 alignment = <0 0x2000000>; 66 reg = <0xf 0xfe124000 0 0x2000>; 67 ranges = <0 0 0xf 0xe8000000 0x08000000 68 1 0 0xf 0xff800000 0x00010000>; 70 nor@0,0 { [all …]
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H A D | p5020ds.dts | 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 76 size = <0 0x2000000>; 77 alignment = <0 0x2000000>; 82 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 86 ranges = <0x0 0xf 0xf4000000 0x200000>; 90 ranges = <0x0 0xf 0xf4200000 0x200000>; 94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | p3041ds.dts | 68 size = <0 0x1000000>; 69 alignment = <0 0x1000000>; 72 size = <0 0x400000>; 73 alignment = <0 0x400000>; 76 size = <0 0x200000 [all...] |
H A D | p1020rdb-pc_36b.dts | 45 reg = <0xf 0xffe05000 0 0x1000>; 48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000 49 0x1 0x0 0xf 0xff800000 0x00040000 50 0x2 0x0 0xf 0xffb00000 0x00040000 51 0x3 0x0 0xf 0xffa00000 0x00020000>; 55 ranges = <0x0 0xf 0xffe00000 0x100000>; 59 reg = <0xf 0xffe09000 0 0x1000>; 60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 62 pcie@0 { [all …]
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H A D | t1024qds.dts | 50 size = <0 0x1000000>; 51 alignment = <0 0x1000000>; 55 size = <0 0x400000>; 56 alignment = <0 0x400000>; 60 size = <0 0x2000000>; 61 alignment = <0 0x2000000>; 66 reg = <0xf 0xfe124000 0 0x2000>; 67 ranges = <0 0 0xf 0xe8000000 0x08000000 68 2 0 0xf 0xff800000 0x00010000 69 3 0 0xf 0xffdf0000 0x00008000>; [all …]
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/freebsd/sys/arm64/include/ |
H A D | armreg.h | 39 #define MRS_MASK 0xfff00000 40 #define MRS_VALUE 0xd5300000 41 #define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 42 #define MRS_REGISTER(insn) ((insn) & 0x0000001f) 44 #define MRS_Op0_MASK 0x00080000 46 #define MRS_Op1_MASK 0x00070000 48 #define MRS_CRn_MASK 0x0000f000 50 #define MRS_CRm_MASK 0x00000f00 52 #define MRS_Op2_MASK 0x000000e0 53 #define MRS_Rt_SHIFT 0 [all …]
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_aic.c | 50 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0 51 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0 54 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000 55 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280 56 #define ATH_AIC_SRAM_CAL_OFFSET 0x140 59 #define ATH_AIC_BT_JUPITER_CTRL 0x66820 60 #define ATH_AIC_BT_AIC_ENABLE 0x02 64 0, 3, 9, 15, 21, 27}; 79 0x00000, // 0 80 0x00000, [all …]
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/freebsd/sys/dev/mii/ |
H A D | micphy.c | 62 #define MII_KSZPHY_EXTREG 0x0b 64 #define MII_KSZPHY_EXTREG_WRITE 0x0c 65 #define MII_KSZPHY_EXTREG_READ 0x0d 66 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 67 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 68 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 70 #define MII_KSZ9031_MMD_ACCESS_CTRL 0x0d 71 #define MII_KSZ9031_MMD_ACCESS_DATA 0x0e 73 #define MII_KSZ9031_CONTROL_PAD_SKEW 0x4 74 #define MII_KSZ9031_RX_DATA_PAD_SKEW 0x5 [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 [all …]
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