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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgp107.c37 .bundle_size = 0x3000,
38 .bundle_min_gpm_fifo_depth = 0x180,
39 .bundle_token_limit = 0x300,
41 .pagepool_size = 0x20000,
45 .attrib_nr_max = 0x15de,
46 .attrib_nr = 0x540,
47 .alpha_nr_max = 0xc00,
48 .alpha_nr = 0x800,
49 .gfxp_nr = 0xe94,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dti,cal.yaml25 # for DRA72 controllers pre ES2.0
75 port@0:
78 description: 'CSI2 Port #0'
112 - port@0
129 reg = <0x4845B000 0x400>,
130 <0x4845B800 0x40>,
131 <0x4845B900 0x40>;
136 ti,camerrx-control = <&scm_conf 0xE94>;
140 #size-cells = <0>;
142 csi2_0: port@0 {
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
50 /* 3. Page8(0x800) */
52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
55 #define rFPGA0_XA_HSSIParameter2 0x824
56 #define rFPGA0_XB_HSSIParameter1 0x828
57 #define rFPGA0_XB_HSSIParameter2 0x82c
58 #define rTxAGC_B_Rate18_06 0x830
[all …]
/linux/drivers/dma/
H A Dste_dma40_ll.h10 #define D40_DREG_PCBASE 0x400
35 #define D40_SREG_CFG_PHY_EVTL_POS 0
40 #define D40_SREG_ELEM_PHY_EIDX_POS 0
42 #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
45 #define D40_SREG_LNK_PHY_TCP_POS 0
52 #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
60 #define D40_SREG_ELEM_LOG_TCP_POS 0
62 #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
66 #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
72 #define D40_MEM_LCSP0_SPTR_POS 0
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dphy.c38 u32 original_value = 0, readback_value, bitshift; in rtl8723e_phy_query_rf_reg()
70 u32 original_value = 0, bitshift; in rtl8723e_phy_set_rf_reg()
117 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl8723e_phy_bb_config_1t()
118 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl8723e_phy_bb_config_1t()
119 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl8723e_phy_bb_config_1t()
120 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl8723e_phy_bb_config_1t()
121 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl8723e_phy_bb_config_1t()
122 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
123 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
124 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl8723e_phy_bb_config_1t()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192c/
H A Dphy_common.c24 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92c_phy_query_bb_reg()
59 return 0; in _rtl92c_phy_fw_rf_serial_read()
79 u8 rfpi_enable = 0; in _rtl92c_phy_rf_serial_read()
82 offset &= 0x3f; in _rtl92c_phy_rf_serial_read()
86 return 0xFFFFFFFF; in _rtl92c_phy_rf_serial_read()
115 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_read()
136 offset &= 0x3f; in _rtl92c_phy_rf_serial_write()
138 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92c_phy_rf_serial_write()
140 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_write()
148 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl92c_phy_bb_config_1t()
[all …]
/linux/drivers/staging/media/starfive/camss/
H A Dstf-isp.h19 #define STF_ISP_REG_OFFSET_MAX 0x0fff
23 #define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000
29 #define CSI_EN_S BIT(0)
31 #define ISP_REG_CSIINTS 0x008
33 #define CSI_SHA_M(n) ((n) << 0)
36 #define ISP_REG_CSI_MODULE_CFG 0x010
48 #define CSI_DC_EN BIT(0)
50 #define ISP_REG_SENSOR 0x014
53 #define IMAGER_SEL(n) ((n) << 0)
55 #define ISP_REG_RAW_FORMAT_CFG 0x018
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.h13 #define CORE_ID 0x0
14 #define VER_NUMBER 0x4
15 #define VER_TYPE 0x8
16 #define CONFIG_REG 0xc
19 #define CORE_TIMESTAMP_HHMM 0x14
20 #define CORE_TIMESTAMP_MMDD 0x18
21 #define CORE_TIMESTAMP_YYYY 0x1c
23 #define GLOBAL_SWRESET_REQUEST 0x40
26 #define GLOBAL_SWDISABLE 0x44
30 #define RESET_MANAGER_CONFIG0 0x48
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dphy.c91 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl8723be_phy_mac_config()
106 regval | BIT(13) | BIT(0) | BIT(1)); in rtl8723be_phy_bb_config()
112 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl8723be_phy_bb_config()
113 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl8723be_phy_bb_config()
115 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723be_phy_bb_config()
120 crystalcap = crystalcap & 0x3F; in rtl8723be_phy_bb_config()
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
140 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); in _rtl8723be_check_positive()
142 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ in _rtl8723be_check_positive()
150 0 << 20 | /* interface 2/2 */ in _rtl8723be_check_positive()
[all …]
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-stm.c37 #define STMDMASTARTR 0xc04
38 #define STMDMASTOPR 0xc08
39 #define STMDMASTATR 0xc0c
40 #define STMDMACTLR 0xc10
41 #define STMDMAIDR 0xcfc
42 #define STMHEER 0xd00
43 #define STMHETER 0xd20
44 #define STMHEBSR 0xd60
45 #define STMHEMCR 0xd64
46 #define STMHEMASTR 0xdf4
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dphy_common.c29 u8 rfpi_enable = 0; in _rtl92d_phy_rf_serial_read()
60 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", in _rtl92d_phy_rf_serial_read()
77 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92d_phy_rf_serial_write()
79 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92d_phy_rf_serial_write()
114 if (bitmask == 0) in rtl92d_phy_set_rf_reg()
141 /* 16 LSBs if read 32-bit from 0x870 */ in rtl92d_phy_init_bb_rf_register_definition()
143 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ in rtl92d_phy_init_bb_rf_register_definition()
145 /* 16 LSBs if read 32-bit from 0x874 */ in rtl92d_phy_init_bb_rf_register_definition()
147 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ in rtl92d_phy_init_bb_rf_register_definition()
151 /* 16 LSBs if read 32-bit from 0x8E0 */ in rtl92d_phy_init_bb_rf_register_definition()
[all …]
H A Ddm_common.c13 0x7f8001fe, /* 0, +6.0dB */
14 0x788001e2, /* 1, +5.5dB */
15 0x71c001c7, /* 2, +5.0dB */
16 0x6b8001ae, /* 3, +4.5dB */
17 0x65400195, /* 4, +4.0dB */
18 0x5fc0017f, /* 5, +3.5dB */
19 0x5a400169, /* 6, +3.0dB */
20 0x55400155, /* 7, +2.5dB */
21 0x50800142, /* 8, +2.0dB */
22 0x4c000130, /* 9, +1.5dB */
[all …]
H A Dreg.h8 /* 0x0000h ~ 0x00FFh System Configuration */
10 #define REG_SYS_ISO_CTRL 0x0000
11 #define REG_SYS_FUNC_EN 0x0002
12 #define REG_APS_FSMCO 0x0004
13 #define REG_SYS_CLKR 0x0008
14 #define REG_9346CR 0x000A
15 #define REG_EE_VPD 0x000C
16 #define REG_AFE_MISC 0x0010
17 #define REG_SPS0_CTRL 0x0011
18 #define REG_POWER_OFF_IN_PROCESS 0x0017
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dphy.c52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, in rtl88e_phy_query_bb_reg()
148 u8 rfpi_enable = 0; in _rtl88e_phy_rf_serial_read()
151 offset &= 0xff; in _rtl88e_phy_rf_serial_read()
155 return 0xFFFFFFFF; in _rtl88e_phy_rf_serial_read()
182 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_read()
201 offset &= 0xff; in _rtl88e_phy_rf_serial_write()
203 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl88e_phy_rf_serial_write()
206 "RFW-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_write()
215 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl88e_phy_mac_config()
229 regval | BIT(13) | BIT(0) | BIT(1)); in rtl88e_phy_bb_config()
[all …]
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_SYS_SWR_CTRL1 0x0010
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_AFE_MISC 0x0010
[all …]
H A Dtable.c7 0x800, 0x8020D010,
8 0x804, 0x080112E0,
9 0x808, 0x0E028233,
10 0x80C, 0x12131113,
11 0x810, 0x20101263,
12 0x814, 0x020C3D10,
13 0x818, 0x03A00385,
14 0x820, 0x00000000,
15 0x824, 0x00030FE0,
16 0x828, 0x00000000,
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c_table.c10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F9,
15 0x420, 0x00000080,
16 0x421, 0x0000001F,
17 0x428, 0x0000000A,
18 0x429, 0x00000010,
19 0x430, 0x00000000,
[all …]
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
H A Drtw8814a_table.c10 0x010, 0x0000007C,
11 0x014, 0x000000DB,
12 0x016, 0x00000002,
13 0x073, 0x00000010,
14 0x420, 0x00000080,
15 0x421, 0x0000000F,
16 0x428, 0x0000000A,
17 0x429, 0x00000010,
18 0x430, 0x00000000,
19 0x431, 0x00000000,
[all …]