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/linux/Documentation/devicetree/bindings/goldfish/
H A Dbattery.txt15 reg = <0x9020000 0x1000>;
16 interrupts = <0x3>;
/linux/Documentation/devicetree/bindings/firmware/
H A Dqemu,fw-cfg-mmio.yaml34 * Bytes 0x0 to 0x7 cover the data register.
35 * Bytes 0x8 to 0x9 cover the selector register.
52 reg = <0x9020000 0xa>;
/linux/drivers/firmware/
H A Dqemu_fw_cfg.c25 * qemu_fw_cfg.ioport=12@0x510:0:1:4 (the default on x86)
27 * qemu_fw_cfg.mmio=16@0x9020000:8:0:16 (the default on arm)
84 if ((ctrl & ~FW_CFG_DMA_CTL_ERROR) == 0) in fw_cfg_wait_for_control()
105 .address = cpu_to_be64(address ? virt_to_phys(address) : 0), in fw_cfg_dma_transfer()
144 memset(buf, 0, count); in fw_cfg_read_blob()
150 while (pos-- > 0) in fw_cfg_read_blob()
179 if (pos == 0) { in fw_cfg_write_blob()
186 if (ret < 0) in fw_cfg_write_blob()
215 # define FW_CFG_CTRL_OFF 0x08
216 # define FW_CFG_DATA_OFF 0x00
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