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/linux/drivers/media/pci/mgb4/
H A Dmgb4_cmt.c19 …{0x1208, 0x0000, 0x171C, 0x0000, 0x1E38, 0x0000, 0x11C7, 0x0000, 0x1041, 0x01BC, 0x7C01, 0x7DE9, 0…
20 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x130D, 0x0080, 0x0041, 0x0090, 0x7C01, 0x7DE9, 0…
21 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x165A, 0x0080, 0x0082, 0x00FA, 0x7C01, 0x7DE9, 0…
22 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x1187, 0x0080, 0x1041, 0x01EE, 0x7C01, 0x7DE9, 0…
23 …{0x1186, 0x0000, 0x1555, 0x0000, 0x1AAA, 0x0000, 0x1451, 0x0000, 0x0042, 0x0013, 0x7C01, 0x7DE9, 0…
24 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x134E, 0x0080, 0x0041, 0x005E, 0x7C01, 0x7DE9, 0…
25 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x1619, 0x0080, 0x0083, 0x00FA, 0x7C01, 0x7DE9, 0…
26 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179E, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
27 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179F, 0x0080, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
28 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x17DF, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dralink,rt3883-pci.txt38 address. The value must be 0. As such, 'interrupt-map' nodes do not
53 address. The value must be 0.
105 reg = <0x10140000 0x20000>;
114 #address-cells = <0>;
128 bus-range = <0 255>;
130 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
134 interrupt-map-mask = <0xf800 0 0 7>;
137 0x8800 0 0 1 &pciintc 18
138 0x8800 0 0 2 &pciintc 18
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
H A Dmpc8572ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00060000>;
77 reg = <0x07f60000 0x00020000>;
[all …]
/linux/sound/soc/codecs/
H A Drt274.h14 #define RT274_AUDIO_FUNCTION_GROUP 0x01
15 #define RT274_DAC_OUT0 0x02
16 #define RT274_DAC_OUT1 0x03
17 #define RT274_ADC_IN2 0x08
18 #define RT274_ADC_IN1 0x09
19 #define RT274_DIG_CVT 0x0a
20 #define RT274_DMIC1 0x12
21 #define RT274_DMIC2 0x13
22 #define RT274_MIC 0x19
23 #define RT274_LINE1 0x1a
[all …]
H A Drt286.h14 #define RT286_AUDIO_FUNCTION_GROUP 0x01
15 #define RT286_DAC_OUT1 0x02
16 #define RT286_DAC_OUT2 0x03
17 #define RT286_ADC_IN1 0x09
18 #define RT286_ADC_IN2 0x08
19 #define RT286_MIXER_IN 0x0b
20 #define RT286_MIXER_OUT1 0x0c
21 #define RT286_MIXER_OUT2 0x0d
22 #define RT286_DMIC1 0x12
23 #define RT286_DMIC2 0x13
[all …]
H A Drt298.h14 #define RT298_AUDIO_FUNCTION_GROUP 0x01
15 #define RT298_DAC_OUT1 0x02
16 #define RT298_DAC_OUT2 0x03
17 #define RT298_DIG_CVT 0x06
18 #define RT298_ADC_IN1 0x09
19 #define RT298_ADC_IN2 0x08
20 #define RT298_MIXER_IN 0x0b
21 #define RT298_MIXER_OUT1 0x0c
22 #define RT298_MIXER_OUT2 0x0d
23 #define RT298_DMIC1 0x12
[all …]
/linux/include/linux/
H A Dscx200.h13 #define scx200_cb_present() (scx200_cb_base!=0)
16 #define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */
17 #define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */
20 #define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */
23 #define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */
26 #define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */
27 #define SCx200_WDT_SIZE 0x05 /* size */
29 #define SCx200_WDT_WDTO 0x00 /* Time-Out Register */
30 #define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */
31 #define SCx200_WDT_WDSTS 0x04 /* Status Register */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
/linux/arch/mips/mm/
H A Dsc-ip22.c24 #define SC_SIZE 0x00080000
39 " li $1, 0x80 # Go 64 bit \n" in indy_sc_wipe()
43 " # Open code a dli $1, 0x9000000080000000 \n" in indy_sc_wipe()
49 " lui $1,0x9000 \n" in indy_sc_wipe()
50 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
51 " ori $1,$1,0x8000 \n" in indy_sc_wipe()
52 " dsll $1,$1,0x10 \n" in indy_sc_wipe()
54 " or %0, $1 # first line to flush \n" in indy_sc_wipe()
58 "1: sw $0, 0(%0) \n" in indy_sc_wipe()
59 " bne %0, %1, 1b \n" in indy_sc_wipe()
[all …]
/linux/drivers/clk/qcom/
H A Dturingcc-qcs404.c24 .halt_reg = 0x5098,
27 .enable_reg = 0x5098,
28 .enable_mask = BIT(0),
37 .halt_reg = 0x9000,
40 .enable_reg = 0x9000,
41 .enable_mask = BIT(0),
50 .halt_reg = 0xb000,
53 .enable_reg = 0xb000,
54 .enable_mask = BIT(0),
63 .halt_reg = 0x10000,
[all …]
/linux/sound/pci/au88x0/
H A Dau8820.h19 #define NR_ADB 0x10
20 #define NR_WT 0x20
21 #define NR_SRC 0x10
22 #define NR_A3D 0x00
23 #define NR_MIXIN 0x10
24 #define NR_MIXOUT 0x10
28 #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
29 #define POS_MASK 0x00000fff
30 #define POS_SHIFT 0x0
31 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/linux/arch/alpha/kernel/
H A Dpci_impl.h18 * Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
19 * IO space areas allocated *before* 0xC000; this is because certain
21 * accesses to probe the bus. If a device's registers appear at 0xC000,
26 #define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */
27 #define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */
107 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
137 #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */
138 #define IOMMU_RESERVED_PTE 0xface
161 #define pci_restore_srm_config() do {} while (0)
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x1>;
108 reg = <0x2>;
114 reg = <0x3>;
120 reg = <0x100>;
128 reg = <0x101>;
134 reg = <0x102>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,msm8998-gpucc.yaml52 reg = <0x05065000 0x9000>;
H A Dqcom,sm6125-gpucc.yaml57 reg = <0x05990000 0x9000>;
H A Dqcom,sm6115-gpucc.yaml49 reg = <0x05990000 0x9000>;
H A Dqcom,qcm2290-gpucc.yaml65 reg = <0x0 0x05990000 0x0 0x9000>;
H A Dqcom,sm6375-gpucc.yaml63 reg = <0 0x05990000 0 0x9000>;
/linux/sound/soc/qcom/
H A Dlpass-sc7280.c114 int chan = 0; in sc7280_lpass_alloc_dma_channel()
193 return 0; in sc7280_lpass_free_dma_channel()
210 for (i = 0; i < drvdata->num_clks; i++) in sc7280_lpass_init()
225 return 0; in sc7280_lpass_init()
233 return 0; in sc7280_lpass_exit()
248 return 0; in sc7280_lpass_dev_suspend()
256 .i2sctrl_reg_base = 0x1000,
257 .i2sctrl_reg_stride = 0x1000,
259 .irq_reg_base = 0x9000,
260 .irq_reg_stride = 0x1000,
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/arch/arm/mach-omap2/
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
/linux/arch/arm/kernel/
H A Dinsn.c17 return 0; in __arm_gen_branch_thumb2()
20 s = (offset >> 24) & 0x1; in __arm_gen_branch_thumb2()
21 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
22 i2 = (offset >> 22) & 0x1; in __arm_gen_branch_thumb2()
23 imm10 = (offset >> 12) & 0x3ff; in __arm_gen_branch_thumb2()
24 imm11 = (offset >> 1) & 0x7ff; in __arm_gen_branch_thumb2()
29 first = 0xf000 | (s << 10) | imm10; in __arm_gen_branch_thumb2()
30 second = 0x9000 | (j1 << 13) | (j2 << 11) | imm11; in __arm_gen_branch_thumb2()
40 unsigned long opcode = 0xea000000; in __arm_gen_branch_arm()
49 return 0; in __arm_gen_branch_arm()
[all …]

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