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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc.h16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
H A Ddpcs_3_1_4_sh_mask.h33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0
34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1
35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2
36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3
37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4
38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7
39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8
40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9
41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa
42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb
[all …]
H A Ddpcs_4_2_2_sh_mask.h14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
H A Ddpcs_4_2_0_sh_mask.h27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
H A Ddpcs_3_0_0_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux/lib/crypto/arm64/
H A Dpoly1305-armv8.pl34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
81 mov $s1,#0xfffffffc0fffffff
82 movk $s1,#0x0fff,lsl#48
87 and $r0,$r0,$s1 // &=0ffffffc0fffffff
89 and $r1,$r1,$s1 // &=0ffffffc0ffffffc
148 cmp x17,#0 // is_base2_26?
236 cmp $r0,#0 // is_base2_26?
265 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
316 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
[all …]
H A Dsha256-ce.S56 .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
57 .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
58 .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
59 .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
60 .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
61 .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
62 .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
63 .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
64 .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
65 .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
[all …]
/linux/arch/arm64/crypto/
H A Daes-modes.S55 frame_push 0
85 frame_push 0
182 frame_push 0
248 add x9, x8, #32
250 sub x9, x9, x4
252 ld1 {v4.16b}, [x9]
277 add x9, x8, #32
279 sub x9, x9, x4
281 ld1 {v4.16b}, [x9]
306 .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
60 #size-cells = <0>;
62 i2c@0 {
63 reg = <0>;
65 #size-cells = <0>;
69 reg = <0x9>;
81 #size-cells = <0>;
85 reg = <0x9>;
97 #size-cells = <0>;
[all …]
/linux/lib/crypto/arm/
H A Dchacha-scalar-core.S14 * (x8, x9) to the stack and swap them out with (x10, x11). This adds one
24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such
38 X9_X11 .req r9 // shared by x9 and x11
106 // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13)
109 // save (x8, x9); restore (x10, x11)
110 __strd X8_X10, X9_X11, sp, 0
124 // save (x10, x11); restore (x8, x9)
126 __ldrd X8_X10, X9_X11, sp, 0
128 // quarterrounds: (x2, x7, x8, x13) and (x3, x4, x9, x14)
133 .set brot, 0
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/arch/arm64/mm/
H A Dproc.S36 #define TCR_KASLR_FLAGS 0
45 #define TCR_KASAN_SW_FLAGS 0
57 #define TCR_MTE_FLAGS 0
87 mrs x9, mdscr_el1
95 stp x8, x9, [x0, #48]
115 ldp x9, x10, [x0, #48]
135 msr vbar_el1, x9
210 tbz \type, #0, .Lnext_\type // Skip invalid and
260 end_pudp .req x9
290 __idmap_cpu_set_reserved_ttbr1 x8, x9
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_sh_mask.h28 …T_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
29 …T_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
30 …T_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
31 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
32 …_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
33 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
34 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
35 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15
36 …_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16
37 …_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_enum.h28 DC_IH_SRC_ID_START = 0x1,
29 DC_IH_SRC_ID_END = 0x1f,
30 VGA_IH_SRC_ID_START = 0x20,
31 VGA_IH_SRC_ID_END = 0x27,
32 CAP_IH_SRC_ID_START = 0x28,
33 CAP_IH_SRC_ID_END = 0x2f,
34 VIP_IH_SRC_ID_START = 0x30,
35 VIP_IH_SRC_ID_END = 0x3f,
36 ROM_IH_SRC_ID_START = 0x40,
37 ROM_IH_SRC_ID_END = 0x5d,
[all …]
H A Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_sh_mask.h29 …P_CTRL__STANDARD__SHIFT 0x0
30 …P_CTRL__STD_VERSION__SHIFT 0x4
31 …STANDARD_MASK 0x0000000FL
32 …STD_VERSION_MASK 0x00000010L
34 …C_GATE__SYS__SHIFT 0x0
35 …C_GATE__UDEC__SHIFT 0x1
36 …C_GATE__MPEG2__SHIFT 0x2
37 …C_GATE__REGS__SHIFT 0x3
38 …C_GATE__RBC__SHIFT 0x4
39 …C_GATE__LMI_MC__SHIFT 0x5
[all …]
H A Dvcn_4_0_5_sh_mask.h30 …C_GATE__SYS__SHIFT 0x0
31 …C_GATE__UDEC__SHIFT 0x1
32 …C_GATE__MPEG2__SHIFT 0x2
33 …C_GATE__REGS__SHIFT 0x3
34 …C_GATE__RBC__SHIFT 0x4
35 …C_GATE__LMI_MC__SHIFT 0x5
36 …C_GATE__LMI_UMC__SHIFT 0x6
37 …C_GATE__IDCT__SHIFT 0x7
38 …C_GATE__MPRD__SHIFT 0x8
39 …C_GATE__MPC__SHIFT 0x9
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_sh_mask.h27 …_PF_MM_INDEX__MM_OFFSET__SHIFT 0x0
28 …PF_MM_INDEX__MM_APER__SHIFT 0x1f
29 …NDEX__MM_OFFSET_MASK 0x7FFFFFFFL
30 …NDEX__MM_APER_MASK 0x80000000L
32 …_PF_MM_DATA__MM_DATA__SHIFT 0x0
33 …ATA__MM_DATA_MASK 0xFFFFFFFFL
35 …_PF_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
36 …NDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
41 …_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0
42 …VLP__SYSHUB_OFFSET_MASK 0x003FFFFFL
[all …]

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