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/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml98 reg = <0 0x00784000 0 0x8ff>,
99 <0 0x00780000 0 0x7a0>,
100 <0 0x00782000 0 0x100>,
101 <0 0x00786000 0 0x1fff>;
110 reg = <0x25b 0x1>;
123 reg = <0 0x00784000 0 0x8ff>;
128 reg = <0x1eb 0x1>;
/linux/drivers/mfd/
H A Dtimberdale.h23 #define TIMB_REV_MAJOR 0x00
24 #define TIMB_REV_MINOR 0x04
25 #define TIMB_HW_CONFIG 0x08
26 #define TIMB_SW_RST 0x40
29 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
31 #define TIMB_HW_VER_MASK 0x0f
32 #define TIMB_HW_VER0 0x00
33 #define TIMB_HW_VER1 0x01
34 #define TIMB_HW_VER2 0x02
35 #define TIMB_HW_VER3 0x03
[all …]
/linux/drivers/ssb/
H A Ddriver_gige.c116 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_read_config()
146 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_write_config()
185 dev->pci_controller.io_map_base = 0x800; in ssb_gige_probe()
190 dev->io_resource.start = 0x800; in ssb_gige_probe()
191 dev->io_resource.end = 0x8FF; in ssb_gige_probe()
195 ssb_device_enable(sdev, 0); in ssb_gige_probe()
200 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); in ssb_gige_probe()
204 dev->mem_resource.end = base + 0x10000 - 1; in ssb_gige_probe()
218 gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); in ssb_gige_probe()
231 dev->has_rgmii = 0; in ssb_gige_probe()
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml43 '^opp-?[0-9]+$':
58 0: MSM8996, speedbin 0
65 0-3: unused
66 4: MSM8996SG, speedbin 0
72 0: IPQ8062
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
97 '^opp-?[0-9]+$':
113 #size-cells = <0>;
115 CPU0: cpu@0 {
118 reg = <0x0 0x0>;
[all …]
/linux/drivers/ata/
H A Dahci_imx.c30 IMX_TIMER1MS = 0x00e0,
32 IMX_P0PHYCR = 0x0178,
39 IMX_P0PHYSR = 0x017c,
41 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
43 IMX_LANE0_OUT_STAT = 0x2003,
46 IMX_CLOCK_RESET = 0x7f3f,
47 IMX_CLOCK_RESET_RESET = 1 << 0,
49 IMX8QM_SATA_AHCI_PTC = 0xc8,
50 IMX8QM_SATA_AHCI_PTC_RXWM_MASK = GENMASK(6, 0),
51 IMX8QM_SATA_AHCI_PTC_RXWM = 0x29,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
[all …]
H A Dgmc_8_2_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h28 DBG_BLOCK_ID_RESERVED = 0x0,
29 DBG_BLOCK_ID_DBG = 0x1,
30 DBG_BLOCK_ID_VMC = 0x2,
31 DBG_BLOCK_ID_PDMA = 0x3,
32 DBG_BLOCK_ID_CG = 0x4,
33 DBG_BLOCK_ID_SRBM = 0x5,
34 DBG_BLOCK_ID_GRBM = 0x6,
35 DBG_BLOCK_ID_RLC = 0x7,
36 DBG_BLOCK_ID_CSC = 0x8,
37 DBG_BLOCK_ID_SEM = 0x9,
[all …]
H A Dsmu_7_1_2_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x2c
34 #define RCU_SAM_RTL_BYTES 0x2c
35 #define RCU_SMU_BYTES 0x14
36 #define RCU_SMU_RTL_BYTES 0x14
[all …]
H A Dsmu_7_1_1_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x80
30 #define RCU_CCF_BITS0 0x1000
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x0
34 #define RCU_SAM_RTL_BYTES 0x0
35 #define RCU_SMU_BYTES 0x0
36 #define RCU_SMU_RTL_BYTES 0x0
[all …]
H A Dsmu_7_1_0_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x28
30 #define RCU_CCF_BITS0 0x500
31 #define RCU_CCF_DWORDS1 0x7f
32 #define RCU_CCF_BITS1 0x1000
33 #define RCU_SAM_BYTES 0x40
34 #define RCU_SAM_RTL_BYTES 0x40
35 #define KEYS_CHAIN_ADR 0x0
36 #define SAMU_KEY_SADR 0xa0
[all …]
H A Dsmu_7_1_3_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_SAM_BYTES 0x2c
32 #define RCU_SAM_RTL_BYTES 0x2c
33 #define RCU_SMU_BYTES 0x14
34 #define RCU_SMU_RTL_BYTES 0x14
35 #define SFP_CHAIN_ADDR 0x1
36 #define SFP_SADR 0x0
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_paired_singles.c24 #define dprintk(...) do { } while(0);
63 #define OP_63_FCMPU 0
91 #define OP_4X_PS_CMPU0 0
125 #define SCALAR_NONE 0
126 #define SCALAR_HIGH (1 << 0)
131 #define GQR_ST_TYPE_MASK 0x00000007
132 #define GQR_ST_TYPE_SHIFT 0
133 #define GQR_ST_SCALE_MASK 0x00003f00
135 #define GQR_LD_TYPE_MASK 0x00070000
137 #define GQR_LD_SCALE_MASK 0x3f000000
[all …]
/linux/drivers/scsi/
H A Dnsp32.c45 static int trans_mode = 0; /* default: BIOS */
46 module_param (trans_mode, int, 0);
47 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
51 static bool auto_param = 0; /* default: ON */
52 module_param (auto_param, bool, 0);
53 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
56 module_param (disc_priv, bool, 0);
57 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
126 {0,0,},
140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/arch/x86/kvm/vmx/
H A Dnested.c25 static bool __read_mostly nested_early_check = 0;
74 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); in init_vmcs_shadow_fields()
75 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); in init_vmcs_shadow_fields()
77 for (i = j = 0; i < max_shadow_read_only_fields; i++) { in init_vmcs_shadow_fields()
98 for (i = j = 0; i < max_shadow_read_write_fields; i++) { in init_vmcs_shadow_fields()
240 hv_vcpu->nested.vm_id = 0; in nested_release_evmcs()
241 hv_vcpu->nested.vp_id = 0; in nested_release_evmcs()
314 vcpu->arch.regs_dirty = 0; in vmx_switch_vmcs()
391 unsigned long roots = 0; in nested_ept_invalidate_addr()
397 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { in nested_ept_invalidate_addr()
[all …]
H A Dvmx.c120 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
132 static bool __read_mostly dump_invalid_vmcs = 0;
138 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
257 return 0; in vmx_setup_l1d_flush()
262 return 0; in vmx_setup_l1d_flush()
267 return 0; in vmx_setup_l1d_flush()
306 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { in vmx_setup_l1d_flush()
323 return 0; in vmx_setup_l1d_flush()
331 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { in vmentry_l1d_flush_parse()
345 if (l1tf < 0) in vmentry_l1d_flush_set()
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
[all …]
/linux/drivers/media/i2c/
H A Dadv7842.c13 * ADV7842 I2C Register Maps, Rev. 0, November 2010
16 * Decoder and Digitizer , Rev. 0, January 2011
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
61 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
68 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
156 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++) in adv7842_check_dv_timings()
[all …]

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