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/linux/arch/loongarch/include/asm/
H A Dkvm_eiointc.h17 #define EIOINTC_BASE 0x1400
18 #define EIOINTC_SIZE 0x900
20 #define EIOINTC_NODETYPE_START 0xa0
21 #define EIOINTC_NODETYPE_END 0xbf
22 #define EIOINTC_IPMAP_START 0xc0
23 #define EIOINTC_IPMAP_END 0xc7
24 #define EIOINTC_ENABLE_START 0x200
25 #define EIOINTC_ENABLE_END 0x21f
26 #define EIOINTC_BOUNCE_START 0x280
27 #define EIOINTC_BOUNCE_END 0x29f
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/linux/drivers/ssb/
H A Ddriver_gige.c116 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_read_config()
146 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0)) in ssb_gige_pci_write_config()
185 dev->pci_controller.io_map_base = 0x800; in ssb_gige_probe()
190 dev->io_resource.start = 0x800; in ssb_gige_probe()
191 dev->io_resource.end = 0x8FF; in ssb_gige_probe()
195 ssb_device_enable(sdev, 0); in ssb_gige_probe()
200 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); in ssb_gige_probe()
204 dev->mem_resource.end = base + 0x10000 - 1; in ssb_gige_probe()
218 gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); in ssb_gige_probe()
231 dev->has_rgmii = 0; in ssb_gige_probe()
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml43 '^opp-?[0-9]+$':
58 0: MSM8996, speedbin 0
65 0-3: unused
66 4: MSM8996SG, speedbin 0
72 0: IPQ8062
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
97 '^opp-?[0-9]+$':
113 #size-cells = <0>;
115 CPU0: cpu@0 {
118 reg = <0x0 0x0>;
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/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
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H A Dgmc_8_2_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
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H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
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H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
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/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h28 DBG_BLOCK_ID_RESERVED = 0x0,
29 DBG_BLOCK_ID_DBG = 0x1,
30 DBG_BLOCK_ID_VMC = 0x2,
31 DBG_BLOCK_ID_PDMA = 0x3,
32 DBG_BLOCK_ID_CG = 0x4,
33 DBG_BLOCK_ID_SRBM = 0x5,
34 DBG_BLOCK_ID_GRBM = 0x6,
35 DBG_BLOCK_ID_RLC = 0x7,
36 DBG_BLOCK_ID_CSC = 0x8,
37 DBG_BLOCK_ID_SEM = 0x9,
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H A Dsmu_7_1_2_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x2c
34 #define RCU_SAM_RTL_BYTES 0x2c
35 #define RCU_SMU_BYTES 0x14
36 #define RCU_SMU_RTL_BYTES 0x14
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H A Dsmu_7_1_1_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x80
30 #define RCU_CCF_BITS0 0x1000
31 #define RCU_CCF_DWORDS1 0x0
32 #define RCU_CCF_BITS1 0x0
33 #define RCU_SAM_BYTES 0x0
34 #define RCU_SAM_RTL_BYTES 0x0
35 #define RCU_SMU_BYTES 0x0
36 #define RCU_SMU_RTL_BYTES 0x0
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H A Dsmu_7_1_0_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0x28
30 #define RCU_CCF_BITS0 0x500
31 #define RCU_CCF_DWORDS1 0x7f
32 #define RCU_CCF_BITS1 0x1000
33 #define RCU_SAM_BYTES 0x40
34 #define RCU_SAM_RTL_BYTES 0x40
35 #define KEYS_CHAIN_ADR 0x0
36 #define SAMU_KEY_SADR 0xa0
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H A Dsmu_7_1_3_enum.h27 #define CG_SRBM_START_ADDR 0x600
28 #define CG_SRBM_END_ADDR 0x8ff
29 #define RCU_CCF_DWORDS0 0xa0
30 #define RCU_CCF_BITS0 0x1400
31 #define RCU_SAM_BYTES 0x2c
32 #define RCU_SAM_RTL_BYTES 0x2c
33 #define RCU_SMU_BYTES 0x14
34 #define RCU_SMU_RTL_BYTES 0x14
35 #define SFP_CHAIN_ADDR 0x1
36 #define SFP_SADR 0x0
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/linux/arch/powerpc/kvm/
H A Dbook3s_paired_singles.c24 #define dprintk(...) do { } while(0);
63 #define OP_63_FCMPU 0
91 #define OP_4X_PS_CMPU0 0
125 #define SCALAR_NONE 0
126 #define SCALAR_HIGH (1 << 0)
131 #define GQR_ST_TYPE_MASK 0x00000007
132 #define GQR_ST_TYPE_SHIFT 0
133 #define GQR_ST_SCALE_MASK 0x00003f00
135 #define GQR_LD_TYPE_MASK 0x00070000
137 #define GQR_LD_SCALE_MASK 0x3f000000
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/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
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/linux/Documentation/driver-api/media/drivers/
H A Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
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