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Searched +full:0 +full:x89000 (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-1g-1.dtsi11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
17 cell-index = <0x29>;
19 reg = <0xa9000 0x1000>;
25 reg = <0xe2000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xe3000 0x1000>;
38 pcsphy1: ethernet-phy@0 {
39 reg = <0x0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-3.dtsi3 * QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
18 cell-index = <0x29>;
20 reg = <0xa9000 0x1000>;
27 reg = <0xe2000 0x1000>;
36 #size-cells = <0>;
38 reg = <0xe3000 0x1000>;
41 pcsphy1: ethernet-phy@0 {
42 reg = <0x0>;
H A Dqoriq-fman-1-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman-0-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman3-1-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy9: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-0-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy1: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-0-10g-1-best-effort.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
45 cell-index = <0x29>;
47 reg = <0xa9000 0x1000>;
55 reg = <0xe2000 0x1000>;
71 #size-cells = <0>;
73 reg = <0xe3000 0x1000>;
76 pcsphy1: ethernet-phy@0 {
77 reg = <0x0>;
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,mdss.yaml19 pattern: "^display-subsystem@[0-9a-f]+$"
102 "^display-controller@[1-9a-f][0-9a-f]*$":
110 "^dsi@[1-9a-f][0-9a-f]*$":
118 "^phy@[1-9a-f][0-9a-f]*$":
139 "^hdmi-tx@[1-9a-f][0-9a-f]*$":
160 reg = <0x1a00000 0x1000>,
161 <0x1ac8000 0x3000>;
184 reg = <0x01a01000 0x89000>;
188 interrupts = <0>;
203 #size-cells = <0>;
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-qcs8300.c12 #define REG_SIZE 0x1000
34 .io_reg = 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
36 .intr_status_reg = 0xc + REG_SIZE * id, \
37 .intr_target_reg = 0x8 + REG_SIZE * id, \
39 .pull_bit = 0, \
44 .in_bit = 0, \
46 .intr_enable_bit = 0, \
47 .intr_status_bit = 0, \
62 .io_reg = 0, \
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-common-npcm7xx.dtsi17 #clock-cells = <0>;
25 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #clock-cells = <0>;
56 #clock-cells = <0>;
66 ranges = <0x0 0xf0000000 0x00900000>;
70 reg = <0x3fe000 0x1000>;
75 reg = <0x3fc000 0x1000>;
87 reg = <0x3ff000 0x1000>,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
[all …]
H A Dmsm8953.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]