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/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-1g-1.dtsi11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
17 cell-index = <0x29>;
19 reg = <0xa9000 0x1000>;
25 reg = <0xe2000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xe3000 0x1000>;
38 pcsphy1: ethernet-phy@0 {
39 reg = <0x0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-3.dtsi3 * QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x9>;
13 reg = <0x89000 0x1000>;
18 cell-index = <0x29>;
20 reg = <0xa9000 0x1000>;
27 reg = <0xe2000 0x1000>;
36 #size-cells = <0>;
38 reg = <0xe3000 0x1000>;
41 pcsphy1: ethernet-phy@0 {
42 reg = <0x0>;
H A Dqoriq-fman-1-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman-0-1g-1.dtsi2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
59 #size-cells = <0>;
61 reg = <0xe3120 0xee0>;
64 reg = <0x8>;
H A Dqoriq-fman3-1-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy9: ethernet-phy@0 {
73 reg = <0x0>;
H A Dqoriq-fman3-0-1g-1.dtsi2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x9>;
39 reg = <0x89000 0x1000>;
43 cell-index = <0x29>;
45 reg = <0xa9000 0x1000>;
51 reg = <0xe2000 0x1000>;
67 #size-cells = <0>;
69 reg = <0xe3000 0x1000>;
72 pcsphy1: ethernet-phy@0 {
73 reg = <0x0>;
/linux/drivers/clk/qcom/
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]