Searched +full:0 +full:x89000 (Results 1 – 18 of 18) sorted by relevance
11 cell-index = <0x9>;13 reg = <0x89000 0x1000>;17 cell-index = <0x29>;19 reg = <0xa9000 0x1000>;25 reg = <0xe2000 0x1000>;34 #size-cells = <0>;36 reg = <0xe3000 0x1000>;38 pcsphy1: ethernet-phy@0 {39 reg = <0x0>;
3 * QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x400000 ]11 cell-index = <0x9>;13 reg = <0x89000 0x1000>;18 cell-index = <0x29>;20 reg = <0xa9000 0x1000>;27 reg = <0xe2000 0x1000>;36 #size-cells = <0>;38 reg = <0xe3000 0x1000>;41 pcsphy1: ethernet-phy@0 {42 reg = <0x0>;
2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;59 #size-cells = <0>;61 reg = <0xe3120 0xee0>;64 reg = <0x8>;
2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;59 #size-cells = <0>;61 reg = <0xe3120 0xee0>;64 reg = <0x8>;
2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;45 cell-index = <0x29>;47 reg = <0xa9000 0x1000>;55 reg = <0xe2000 0x1000>;71 #size-cells = <0>;73 reg = <0xe3000 0x1000>;76 pcsphy1: ethernet-phy@0 {77 reg = <0x0>;
2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;67 #size-cells = <0>;69 reg = <0xe3000 0x1000>;72 pcsphy1: ethernet-phy@0 {73 reg = <0x0>;
2 * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;67 #size-cells = <0>;69 reg = <0xe3000 0x1000>;72 pcsphy9: ethernet-phy@0 {73 reg = <0x0>;
19 pattern: "^display-subsystem@[0-9a-f]+$"102 "^display-controller@[1-9a-f][0-9a-f]*$":110 "^dsi@[1-9a-f][0-9a-f]*$":118 "^phy@[1-9a-f][0-9a-f]*$":139 "^hdmi-tx@[1-9a-f][0-9a-f]*$":160 reg = <0x1a00000 0x1000>,161 <0x1ac8000 0x3000>;184 reg = <0x01a01000 0x89000>;188 interrupts = <0>;203 #size-cells = <0>;[all …]
28 FMan block. The offset is 0xc4 from the beginning of the29 Frame Processing Manager memory map (0xc3000 from the44 DEVDISR[1] 1 049 DCFG_DEVDISR2[6] 1 056 DCFG_CCSR_DEVDISR2[24] 1 0148 muram@0 {150 ranges = <0 0x000000 0x28000>;215 cell-index = <0x28>;217 reg = <0xa8000 0x1000>;221 cell-index = <0x8>;[all …]
17 #clock-cells = <0>;25 #clock-cells = <0>;33 #clock-cells = <0>;41 #clock-cells = <0>;49 #clock-cells = <0>;56 #clock-cells = <0>;66 ranges = <0x0 0xf0000000 0x00900000>;70 reg = <0x3fe00[all...]
103 #size-cells = <0>;105 cpu0: PowerPC,e500mc@0 {107 reg = <0>;145 dcsr-epu@0 {147 interrupts = <52 2 0 0148 84 2 0 0149 85 2 0 0>;151 reg = <0x0 0x1000>;155 reg = <0x1000 0x1000 0x1000000 0x8000>;159 reg = <0x2000 0x1000>;[all …]
102 #size-cells = <0>;104 cpu0: PowerPC,e500mc@0 {106 reg = <0>;144 dcsr-epu@0 {146 interrupts = <52 2 0 0147 84 2 0 0148 85 2 0 0>;150 reg = <0x0 0x1000>;154 reg = <0x1000 0x1000 0x1000000 0x8000>;158 reg = <0x2000 0x1000>;[all …]
109 #size-cells = <0>;111 cpu0: PowerPC,e5500@0 {113 reg = <0>;135 dcsr-epu@0 {137 interrupts = <52 2 0 0138 84 2 0 0139 85 2 0 0>;141 reg = <0x0 0x1000>;145 reg = <0x1000 0x1000 0x1000000 0x8000>;149 reg = <0x2000 0x1000>;[all …]
26 #clock-cells = <0>;32 #size-cells = <0>;34 CPU0: cpu@0 {37 reg = <0x0>;48 reg = <0x1>;59 reg = <0x2>;70 reg = <0x3>;81 reg = <0x100>;92 reg = <0x101>;103 reg = <0x102>;[all …]
25 #clock-cells = <0>;31 #clock-cells = <0>;39 #size-cells = <0>;41 CPU0: cpu@0 {44 reg = <0x0>;54 reg = <0x1>;64 reg = <0x2>;74 reg = <0x3>;84 reg = <0x100>;94 reg = <0x101>;[all …]
30 #clock-cells = <0>;36 #clock-cells = <0>;43 #size-cells = <0>;49 reg = <0x100>;67 reg = <0x101>;80 reg = <0x102>;93 reg = <0x103>;102 CPU4: cpu@0 {106 reg = <0x0>;124 reg = <0x1>;[all …]
35 #clock-cells = <0>;42 #clock-cells = <0>;50 #size-cells = <0>;55 reg = <0x0 0x100>;75 reg = <0x0 0x101>;90 reg = <0x0 0x102>;105 reg = <0x0 0x103>;117 CPU4: cpu@0 {120 reg = <0x0 0x0>;140 reg = <0x0 0x1>;[all …]
27 reg = <0 0x80000000 0 0>;36 reg = <0x0 0x86000000 0x0 0x300000>;42 reg = <0x0 0x86300000 0x0 0x100000>;50 reg = <0x0 0x86400000 0x0 0x100000>;55 reg = <0x0 0x86500000 0x0 0x180000>;60 reg = <0x0 0x86680000 0x0 0x80000>;66 reg = <0x0 0x86700000 0x0 0xe0000>;73 reg = <0x0 0x867e0000 0x0 0x20000>;85 * alignment = <0x0 0x400000>;86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;[all …]