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/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_mscm.c58 #define MSCM_IRSPRC(n) (0x880 + 2 * n)
67 { SYS_RES_MEMORY, 0, RF_ACTIVE },
68 { -1, 0 }
99 sc->bst = rman_get_bustag(sc->res[0]); in mscm_attach()
100 sc->bsh = rman_get_bushandle(sc->res[0]); in mscm_attach()
103 for (i = 0; i < VF_NINT; i++) in mscm_attach()
106 return (0); in mscm_attach()
112 { 0, 0 }
121 DRIVER_MODULE(mscm, simplebus, mscm_driver, 0, 0);
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dam437x-cm-t43.dts39 pinctrl-0 = <&cm_t43_led_pins>;
43 AM4372_IOPAD(0xa78, MUX_MODE7)
49 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
50 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
56 AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
57 AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
58 AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
59 AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
60 AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
61 AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
[all …]
H A Dam437x-gp-evm.dts57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
68 pinctrl-0 = <&matrix_keypad_default>;
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
103 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddpu-sdm845.yaml65 "^display-controller@[0-9a-f]+$":
118 port@0:
127 - port@0
164 reg = <0x0ae00000 0x1000>;
176 iommus = <&apps_smmu 0x880 0x8>,
177 <&apps_smmu 0xc80 0x8>;
182 reg = <0x0ae01000 0x8f000>,
183 <0x0aeb0000 0x2008>;
193 interrupts = <0>;
199 #size-cells = <0>;
[all …]
H A Dqcom,sdm845-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc8
[all...]
/freebsd/sys/dev/rtwn/rtl8192c/usb/
H A Dr92cu_priv.h29 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
30 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
31 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
32 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
33 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
34 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
35 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
36 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 },
37 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff },
38 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/contrib/device-tree/src/arm/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_priv.h31 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
32 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
33 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
34 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
35 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
36 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
37 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
38 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 },
39 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 },
40 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
[all …]
/freebsd/sys/dts/arm/
H A Dufw.dts38 reg = <0x80000000 0x10000000>; /* 256 MB */
41 vmmcsd_fixed: fixedregulator@0 {
51 pinctrl-0 = <&clkout2_pin>;
55 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
56 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
62 AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */
63 AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */
69 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
70 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
76 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_priv.h39 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
40 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
41 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
42 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
43 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
44 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
45 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
46 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
47 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
48 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
[all …]
/freebsd/sys/arm/mv/
H A Dmvwin.h45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
70 #define MV_PCI_MEM_PHYS_BASE 0x80000000
75 #define MV_PCI_IO_PHYS_BASE 0xBF000000
79 #define MV_PCI_VA_MEM_BASE 0
80 #define MV_PCI_VA_IO_BASE 0
85 #define MV_DEV_BOOT_BASE 0xF9300000
88 #define MV_DEV_CS0_BASE 0xF9400000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-sm1.dtsi16 tdmif_a: audio-controller-0 {
18 #sound-dai-cells = <0>;
29 #sound-dai-cells = <0>;
40 #sound-dai-cells = <0>;
50 #address-cells = <0x2>;
51 #size-cells = <0x0>;
53 cpu0: cpu@0 {
56 reg = <0x0 0x0>;
65 reg = <0x0 0x1>;
74 reg = <0x0 0x2>;
[all …]
/freebsd/sys/dev/rtwn/rtl8192e/
H A Dr92e_priv.h34 { 0x011, 0xeb }, { 0x012, 0x07 }, { 0x014, 0x75 }, { 0x303, 0xa7 },
35 { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x00 },
36 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
37 { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
38 { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d }, { 0x441, 0x01 },
39 { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 }, { 0x446, 0x00 },
40 { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 }, { 0x44a, 0x0f },
41 { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 }, { 0x44e, 0x00 },
42 { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 }, { 0x452, 0x0f },
43 { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 }, { 0x461, 0x66 },
[all …]
/freebsd/sys/dev/tsec/
H A Dif_tsecreg.h29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */
30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */
36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */
37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */
38 #define TSEC_REG_PTV 0x028 /* Pause time value register */
39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */
40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-csr.h27 #define CSR_BASE (0x000)
29 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
31 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
32 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
33 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
34 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
35 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36 #define CSR_GP_CNTRL (CSR_BASE+0x024)
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02
[all...]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/tools/tools/cxgbtool/
H A Dreg_defs.c7 { "SG_CONTROL", 0x0, 0 },
8 { "CmdQ0_Enable", 0, 1 },
24 { "SG_DOORBELL", 0x4, 0 },
25 { "CmdQ0_Enable", 0, 1 },
29 { "SG_CMD0BASELWR", 0x8, 0 },
30 { "SG_CMD0BASEUPR", 0xc, 0 },
31 { "SG_CMD1BASELWR", 0x10, 0 },
32 { "SG_CMD1BASEUPR", 0x14, 0 },
33 { "SG_FL0BASELWR", 0x18, 0 },
34 { "SG_FL0BASEUPR", 0x1c, 0 },
[all …]

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