Home
last modified time | relevance | path

Searched +full:0 +full:x84000 (Results 1 – 25 of 32) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmarvell,kirkwood-pcie.yaml28 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
36 This range entry translates the '0x82000000 0 r' PCI address into the
37 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
38 register window (as identified by MBUS_ID(0xf0, 0x01)).
42 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
132 bus-range = <0x00 0xff>;
136 … <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
137 … 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
138 … 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
139 … 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmarvell,mvebu-sata-phy.yaml28 const: 0
43 reg = <0x84000 0x0334>;
46 #phy-cells = <0>;
H A Dphy-mvebu.txt17 reg = <0x84000 0x0334>;
20 #phy-cells = <0>;
40 reg = <0x18400 0x4>;
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dqoriq-fman3-0.dtsi14 cell-index = <0>;
16 ranges = <0x0 0x0 0x1a00000 0xfe000>;
17 reg = <0x0 0x1a00000 0x0 0xfe000>;
20 clocks = <&clockgen QORIQ_CLK_FMAN 0>;
22 fsl,qman-channel-range = <0x800 0x10>;
26 muram@0 {
28 reg = <0x0 0x60000>;
32 cell-index = <0x2>;
34 reg = <0x82000 0x1000>;
38 cell-index = <0x3>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3l-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x30000>;
54 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Ds800-0-3.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
H A Ds8001.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled in by loader */
40 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled in by loader */
53 i-cache-size = <0x10000>;
[all …]
H A Dt8011.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8010.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
31 cpu0: cpu@0 {
33 reg = <0x0 0x0>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x1>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8012.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
33 reg = <0x0 0x10000>;
34 cpu-release-addr = <0 0>; /* To be filled by loader */
40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
46 reg = <0x0 0x10001>;
47 cpu-release-addr = <0 0>; /* To be filled by loader */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
[all …]
H A Dt8015.dtsi22 #clock-cells = <0>;
29 #size-cells = <0>;
57 cpu_e0: cpu@0 {
59 reg = <0x0 0x0>;
60 cpu-release-addr = <0 0>; /* To be filled by loader */
67 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
73 reg = <0x0 0x1>;
74 cpu-release-addr = <0 0>; /* To be filled by loader */
81 i-cache-size = <0x8000>;
[all …]
H A Dt8011-pmgr.dtsi11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x80008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x80010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x80040 4>;
[all …]
H A Dt8010-pmgr.dtsi11 reg = <0x80000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x80008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x80040 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x80160 4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts38 memory@0 {
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 pinctrl-0 = <&pinctrl_can0_default>;
53 pinctrl-0 = <&pinctrl_can1_default>;
93 pinctrl-0 = <&pinctrl_gem2_default>;
96 #size-cells = <0>;
99 ti,rx-internal-delay = <0x8>;
100 ti,tx-internal-delay = <0xa>;
101 ti,fifo-depth = <0x1>;
115 pinctrl-0 = <&pinctrl_i2c0_default>;
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_priv.h39 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
40 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
41 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
42 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
43 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
44 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
45 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
46 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
47 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
48 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
[all …]

12