Searched +full:0 +full:x80f00000 (Results 1 – 5 of 5) sorted by relevance
15 #size-cells = <0>;17 cpu@0 {19 reg = <0>;26 pll: clock-0 {28 #clock-cells = <0>;34 #clock-cells = <0>;50 reg = <0xb0040000 0x1000>;59 ranges = <0x0 0xc0000000 0x30000000>;64 reg = <0xeff0000 0x1000>;71 reg = <0x80f00000 0x1000>;[all …]
161 mailbox0_cluster3: mailbox-0 {173 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */174 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */175 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */176 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */181 reg = <0x4d 0x80800000 0x00 0x00048000>,182 <0x4d 0x80e00000 0x00 0x00008000>,183 <0x4d 0x80f00000 0x00 0x00008000>;187 ti,sci-proc-ids = <0x03 0xFF>;198 reg = <0x00 0x64800000 0x00 0x00080000>,[all …]
15 #clock-cells = <0>;17 clock-frequency = <0>;21 #clock-cells = <0>;23 clock-frequency = <0>;30 reg = <0x0 0x70000000 0x0 0x800000>;33 ranges = <0x0 0x0 0x70000000 0x800000>;35 atf-sram@0 {36 reg = <0x0 0x20000>;42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */45 ranges = <0x0 0x0 0x00100000 0x1c000>;[all …]
33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 041 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000047 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 049 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF000061 #define PIN_CFG_NA 0x0000000062 #define PIN_CFG_GPIO0_P0 0x0000000163 #define PIN_CFG_GPIO1_P0 0x00000002[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]