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/linux/drivers/mfd/
H A Dwm97xx-core.c23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
52 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
[all …]
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x07_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x08_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
H A Dhw_host1x06_vm.h6 #define HOST1X_CHANNEL_DMASTART 0x0000
7 #define HOST1X_CHANNEL_DMASTART_HI 0x0004
8 #define HOST1X_CHANNEL_DMAPUT 0x0008
9 #define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10 #define HOST1X_CHANNEL_DMAGET 0x0010
11 #define HOST1X_CHANNEL_DMAGET_HI 0x0014
12 #define HOST1X_CHANNEL_DMAEND 0x0018
13 #define HOST1X_CHANNEL_DMAEND_HI 0x001c
14 #define HOST1X_CHANNEL_DMACTRL 0x0020
15 #define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
[all …]
/linux/drivers/scsi/
H A Datp870u.h19 #define ATP885_DEVID 0x808A
20 #define ATP880_DEVID1 0x8080
21 #define ATP880_DEVID2 0x8081
/linux/sound/soc/codecs/
H A Dad1980.c31 { 0x02, 0x8000 },
32 { 0x04, 0x8000 },
33 { 0x06, 0x8000 },
34 { 0x0c, 0x8008 },
35 { 0x0e, 0x8008 },
36 { 0x10, 0x8808 },
37 { 0x12, 0x8808 },
38 { 0x16, 0x8808 },
39 { 0x18, 0x8808 },
40 { 0x1a, 0x0000 },
[all …]
H A Dtlv320aic26.c105 * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal) in aic26_hw_params()
114 qval = 0; in aic26_hw_params()
115 reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; in aic26_hw_params()
122 reg = 0x0800; in aic26_hw_params()
124 reg = 0x2000; in aic26_hw_params()
125 snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL3, 0xf800, reg); in aic26_hw_params()
129 snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL1, 0xfff, reg); in aic26_hw_params()
131 return 0; in aic26_hw_params()
147 reg = 0x8080; in aic26_mute()
[all...]
/linux/Documentation/devicetree/bindings/clock/
H A Damlogic,t7-pll-clkc.yaml99 reg = <0 0x8080 0 0x20>;
107 reg = <0 0x8300 0 0x18>;
/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen4.h9 #define PCI_DEVICE_REVISION_ICX_MIN 0x2
10 #define PCI_DEVICE_REVISION_ICX_MAX 0xF
14 #define GEN4_IMBAR23SZ_OFFSET 0x00c4
15 #define GEN4_IMBAR45SZ_OFFSET 0x00c5
16 #define GEN4_EMBAR23SZ_OFFSET 0x00c6
17 #define GEN4_EMBAR45SZ_OFFSET 0x00c7
18 #define GEN4_DEVCTRL_OFFSET 0x0048
19 #define GEN4_DEVSTS_OFFSET 0x004a
20 #define GEN4_UNCERRSTS_OFFSET 0x0104
21 #define GEN4_CORERRSTS_OFFSET 0x0110
[all …]
/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_ierb.c28 #define ENETC_IERB_TXMBAR(port) (((port) * 0x100) + 0x8080)
29 #define ENETC_IERB_RXMBER(port) (((port) * 0x100) + 0x8090)
30 #define ENETC_IERB_RXMBLR(port) (((port) * 0x100) + 0x8094)
31 #define ENETC_IERB_RXBCR(port) (((port) * 0x100) + 0x80a0)
32 #define ENETC_IERB_TXBCR(port) (((port) * 0x100) + 0x80a8)
33 #define ENETC_IERB_FMBDTR 0xa000
53 if (port < 0) in enetc_ierb_register_pf()
94 return 0; in enetc_ierb_register_pf()
107 regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in enetc_ierb_probe()
126 return 0; in enetc_ierb_probe()
/linux/arch/powerpc/platforms/8xx/
H A Dmicropatch.c40 1, 0x802a, 0x8028, 0x802e, 0x802c,
44 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000,
45 0x5FEFADF7, 0x5F89ADF7, 0x5FEFAFF7, 0x5F89AFF7,
46 0x3A9CFBC8, 0xE7C0EDF0, 0x77C1E1BB, 0xF4DC7F1D,
47 0xABAD932F, 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF,
48 0xFD1FF9CF, 0xABF88DC6, 0xAB5679F7, 0xB0937383,
49 0xDFCE79F7, 0xB091E6BB, 0xE5BBE74F, 0xB3FA6F0F,
50 0x6FFB76CE, 0xEE0DF9CF, 0x2BFBEFEF, 0xCFEEF9CF,
51 0x76CEAD24, 0x90B2DF9A, 0x7FDDD0BF, 0x4BF847FD,
52 0x7CCF76CE, 0xCFEF7E1F, 0x7F1D7DFD, 0xF0B6EF71,
[all …]
/linux/drivers/bcma/
H A Ddriver_pcie2.c19 #if 0
60 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844); in bcma_core_pcie2_set_ltr_vals()
61 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c); in bcma_core_pcie2_set_ltr_vals()
63 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848); in bcma_core_pcie2_set_ltr_vals()
64 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864); in bcma_core_pcie2_set_ltr_vals()
66 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C); in bcma_core_pcie2_set_ltr_vals()
67 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003); in bcma_core_pcie2_set_ltr_vals()
86 *si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); in bcma_core_pcie2_hw_ltr_war()
120 #if 0 in pciedev_crwlpciegen2()
123 #if 0 in pciedev_crwlpciegen2()
[all …]
/linux/drivers/gpu/drm/vkms/
H A Dvkms_luts.c16 { 0x0, 0x0, 0x0, 0 },
17 { 0x101, 0x101, 0x101, 0 },
18 { 0x202, 0x202, 0x202, 0 },
19 { 0x303, 0x303, 0x303, 0 },
20 { 0x404, 0x404, 0x404, 0 },
21 { 0x505, 0x505, 0x505, 0 },
22 { 0x606, 0x606, 0x606, 0 },
23 { 0x707, 0x707, 0x707, 0 },
24 { 0x808, 0x808, 0x808, 0 },
25 { 0x909, 0x909, 0x909, 0 },
[all …]
/linux/include/video/
H A Dmach64.h20 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
21 #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
22 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
23 #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
24 #define CRTC_H_SYNC_STRT 0x0004
25 #define CRTC2_H_SYNC_STRT 0x0004
26 #define CRTC_H_SYNC_DLY 0x0005
27 #define CRTC2_H_SYNC_DLY 0x0005
28 #define CRTC_H_SYNC_WID 0x0006
29 #define CRTC2_H_SYNC_WID 0x0006
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/linux/include/sound/ac97/
H A Dregs.h13 #define AC97_RESET 0x00 /* Reset */
14 #define AC97_MASTER 0x02 /* Master Volume */
15 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
16 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
17 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
18 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */
19 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
20 #define AC97_MIC 0x0e /* MIC Volume */
21 #define AC97_LINE 0x10 /* Line In Volume */
22 #define AC97_CD 0x12 /* CD Volume */
[all …]
/linux/arch/alpha/include/asm/
H A Dcore_mcpcia.h58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x058
[all …]
/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
392 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
397 base = of_iomap(np, 0); in imx7d_clocks_init()
401 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
402 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dhw.c29 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
41 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
43 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
59 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92de_enable_bcn_sub_func()
64 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92de_disable_bcn_sub_func()
99 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92de_set_hw_reg()
103 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92de_set_hw_reg()
139 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92de_set_hw_reg()
145 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
146 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92de_set_hw_reg()
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc0-sa8775p.c57 { 249600000, 2020000000, 0 },
61 .l = 0x3a,
62 .alpha = 0x9800,
63 .config_ctl_val = 0x20485699,
64 .config_ctl_hi_val = 0x00182261,
65 .config_ctl_hi1_val = 0x32aa299c,
66 .user_ctl_val = 0x00000000,
67 .user_ctl_hi_val = 0x00400805,
71 .offset = 0x0,
88 .l = 0x1f,
[all …]
H A Ddispcc1-sa8775p.c57 { 249600000, 2020000000, 0 },
61 .l = 0x3a,
62 .alpha = 0x9800,
63 .config_ctl_val = 0x20485699,
64 .config_ctl_hi_val = 0x00182261,
65 .config_ctl_hi1_val = 0x32aa299c,
66 .user_ctl_val = 0x00000000,
67 .user_ctl_hi_val = 0x00400805,
71 .offset = 0x0,
88 .l = 0x1f,
[all …]
H A Ddispcc-sm8550.c50 #define DISP_CC_MISC_CMD 0xF000
73 { 249600000, 2000000000, 0 },
77 .l = 0xd,
78 .alpha = 0x6492,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x82aa299c,
82 .test_ctl_val = 0x00000000,
83 .test_ctl_hi_val = 0x00000003,
84 .test_ctl_hi1_val = 0x00009000,
[all …]
H A Ddispcc-sm8450.c50 #define DISP_CC_MISC_CMD 0xF000
73 { 249600000, 2000000000, 0 },
77 .l = 0xD,
78 .alpha = 0x6492,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x32AA299C,
82 .user_ctl_val = 0x00000000,
83 .user_ctl_hi_val = 0x00000805,
87 .l = 0xd,
[all …]

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