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12

/linux/drivers/firmware/efi/
H A Dsysfb_efi.c30 OVERRIDE_NONE = 0x0,
31 OVERRIDE_BASE = 0x1,
32 OVERRIDE_STRIDE = 0x2,
33 OVERRIDE_HEIGHT = 0x4,
34 OVERRIDE_WIDTH = 0x8,
38 [M_I17] = { "i17", 0x80010000, 1472 * 4, 1440, 900, OVERRIDE_NONE },
39 [M_I20] = { "i20", 0x80010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE }, /* guess */
40 [M_I20_SR] = { "imac7", 0x40010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE },
41 [M_I24] = { "i24", 0x80010000, 2048 * 4, 1920, 1200, OVERRIDE_NONE }, /* guess */
42 [M_I24_8_1] = { "imac8", 0xc0060000, 2048 * 4, 1920, 1200, OVERRIDE_NONE },
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_table.c11 {0xF0FF0001, 0x00000000},
12 {0xF03300FF, 0x00000001},
13 {0xF03500FF, 0x00000002},
14 {0xF03200FF, 0x00000003},
15 {0xF03400FF, 0x00000004},
16 {0xF03600FF, 0x00000005},
17 {0x704, 0x601E0100},
18 {0x714, 0x00000000},
19 {0x718, 0x13332333},
20 {0x714, 0x00010000},
[all …]
H A Drtw8852b_table.c11 {0x704, 0x601E0100},
12 {0x4000, 0x00000000},
13 {0x4004, 0xCA014000},
14 {0x4008, 0xC751D4F0},
15 {0x400C, 0x44511475},
16 {0x4010, 0x00000000},
17 {0x4014, 0x00000000},
18 {0x4018, 0x4F4C084B},
19 {0x401C, 0x084A4E52},
20 {0x4020, 0x4D504E4B},
[all …]
H A Drtw8852c_table.c11 {0xF0FF0000, 0x00000000},
12 {0xF03300FF, 0x00000001},
13 {0xF03400FF, 0x00000002},
14 {0xF03500FF, 0x00000003},
15 {0xF03600FF, 0x00000004},
16 {0x70C, 0x00000020},
17 {0x704, 0x601E0100},
18 {0x4000, 0x00000000},
19 {0x4004, 0xCA014000},
20 {0x4008, 0xC751D4F0},
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dmxs-spi.yaml53 #size-cells = <0>;
55 reg = <0x80010000 0x2000>;
57 dmas = <&dma_apbh 0>;
/linux/Documentation/devicetree/bindings/net/
H A Dcirrus,ep9301-eth.yaml55 reg = <0x80010000 0x10000>;
/linux/Documentation/devicetree/bindings/mmc/
H A Dmxs-mmc.yaml57 reg = <0x80010000 2000>;
60 dmas = <&dma_apbh 0>;
/linux/arch/arm/boot/dts/st/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
/linux/include/uapi/video/
H A Dsisfb.h33 #define CRT2_DEFAULT 0x00000001
34 #define CRT2_LCD 0x00000002
35 #define CRT2_TV 0x00000004
36 #define CRT2_VGA 0x00000008
37 #define TV_NTSC 0x00000010
38 #define TV_PAL 0x00000020
39 #define TV_HIVISION 0x00000040
40 #define TV_YPBPR 0x00000080
41 #define TV_AVIDEO 0x00000100
42 #define TV_SVIDEO 0x00000200
[all …]
/linux/arch/mips/kernel/
H A Dbmips_vec.S35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
55 li k0, 0xff400000
60 andi k1, 0x8000
63 li k1, 0xa0080000
64 sw k1, 0(k0)
78 * entire function gets copied to 0x8000_0000.
100 /* if we're not on core 0, this must be the SMP boot signal */
134 andi k0, 0xff00
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-dai-adda.c16 AUDIO_SDM_LEVEL_MUTE = 0,
17 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
24 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
25 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
26 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
28 I_ADDA_UL_CH2, 1, 0),
30 I_ADDA_UL_CH1, 1, 0),
32 I_PCM_1_CAP_CH1, 1, 0),
34 I_PCM_2_CAP_CH1, 1, 0),
38 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
[all...]
/linux/arch/arm/boot/dts/cirrus/
H A Dep93xx.dtsi18 reg = <0x80930000 0x1000>;
101 reg = <0x80900000 0x28>;
110 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
116 reg = <0x80080000 0x20>;
125 reg = <0x80000000 0x0040>,
126 <0x80000040 0x0040>,
127 <0x80000080 0x0040>,
128 <0x800000c0 0x0040>,
129 <0x80000240 0x0040>,
130 <0x80000200 0x0040>,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_32.h12 .pvr_mask = 0xffff0000,
13 .pvr_value = 0x00030000,
17 .mmu_features = 0,
25 .pvr_mask = 0xffff0000,
26 .pvr_value = 0x00060000,
30 .mmu_features = 0,
38 .pvr_mask = 0xffff0000,
39 .pvr_value = 0x00070000,
43 .mmu_features = 0,
51 .pvr_mask = 0x7fff0000,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0_3.c37 (offset & 0x1FFFF)
40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),
66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
[all …]
/linux/arch/m68k/fpsp040/
H A Dsetox.S80 | 2.1 Set AdjFlag := 0 (indicates the branch 1.3 -> 2 was taken)
82 | 2.3 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
154 | 6.1 If AdjFlag = 0, go to 6.3
158 | Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R,
189 | 8.3 Calculate J = N mod 64, J = 0,1,...,63
197 | 9.1 If X < 0, go to 9.3
212 | Step 1. Set ans := 0
234 | 2.2 Calculate J = N mod 64; so J = 0,1,2,..., or 63.
343 L2: .long 0x3FDC0000,0x82E30865,0x4361C4C6,0x00000000
345 EXPA3: .long 0x3FA55555,0x55554431
[all …]
H A Dsatan.S55 BOUNDS1: .long 0x3FFB8000,0x4002FFFF
57 ONE: .long 0x3F800000
59 .long 0x00000000
61 ATANA3: .long 0xBFF6687E,0x314987D8
62 ATANA2: .long 0x4002AC69,0x34A26DB3
64 ATANA1: .long 0xBFC2476F,0x4E1DA28E
65 ATANB6: .long 0x3FB34444,0x7F876989
67 ATANB5: .long 0xBFB744EE,0x7FAF45DB
68 ATANB4: .long 0x3FBC71C6,0x46940220
70 ATANB3: .long 0xBFC24924,0x921872F9
[all …]
/linux/drivers/infiniband/hw/qedr/
H A Dqedr_roce_cm.c107 -EINVAL : 0; in qedr_ll2_complete_rx_packet()
110 qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = in qedr_ll2_complete_rx_packet()
112 *((u32 *)&qp->rqe_wr_id[qp->rq.gsi_cons].smac[0]) = in qedr_ll2_complete_rx_packet()
177 return 0; in qedr_check_gsi_qp_attrs()
188 memset(&ll2_tx_pkt, 0, sizeof(ll2_tx_pkt)); in qedr_ll2_post_tx()
197 ll2_tx_pkt.vlan = 0; in qedr_ll2_post_tx()
219 for (i = 0; i < pkt->n_seg; i++) { in qedr_ll2_post_tx()
236 return 0; in qedr_ll2_post_tx()
244 return 0; in qedr_ll2_stop()
276 memset(&data, 0, sizeof(data)); in qedr_ll2_start()
[all …]
/linux/drivers/infiniband/sw/rxe/
H A Drxe_hdr.h69 #define BTH_TVER (0)
70 #define BTH_DEF_PKEY (0xffff)
72 #define BTH_SE_MASK (0x80)
73 #define BTH_MIG_MASK (0x40)
74 #define BTH_PAD_MASK (0x30)
75 #define BTH_TVER_MASK (0x0f)
76 #define BTH_FECN_MASK (0x80000000)
77 #define BTH_BECN_MASK (0x40000000)
78 #define BTH_RESV6A_MASK (0x3f000000)
79 #define BTH_QPN_MASK (0x00ffffff)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dpci.c15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7927),
21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x6639),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0738),
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7928),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7935),
73 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
78 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
119 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
[all …]
/linux/include/hyperv/
H A Dhvgdk_mini.h17 #define HV_STATUS_SUCCESS 0x0
18 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2
19 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3
20 #define HV_STATUS_INVALID_ALIGNMENT 0x4
21 #define HV_STATUS_INVALID_PARAMETER 0x5
22 #define HV_STATUS_ACCESS_DENIED 0x6
23 #define HV_STATUS_INVALID_PARTITION_STATE 0x7
24 #define HV_STATUS_OPERATION_DENIED 0x8
25 #define HV_STATUS_UNKNOWN_PROPERTY 0x9
26 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA
[all …]

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