| /linux/drivers/net/ethernet/broadcom/ |
| H A D | bnx2_fw.h | 17 .state_value_clear = 0xffffff,
24 .mips_view_base = 0x8000000,
33 .state_value_clear = 0xffffff,
40 .mips_view_base = 0x8000000,
49 .state_value_clear = 0xffffff,
56 .mips_view_base = 0x8000000,
65 .state_value_clear = 0xffffff,
72 .mips_view_base = 0x8000000,
81 .state_value_clear = 0xffffff,
88 .mips_view_base = 0x8000000,
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_2_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
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| H A D | gfx_8_0_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
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| H A D | gfx_8_1_sh_mask.h | 27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | flctl-nand.txt | 26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
|
| /linux/arch/riscv/boot/dts/microchip/ |
| H A D | mpfs-m100pfs-fabric.dtsi | 7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
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| H A D | mpfs-polarberry-fabric.dtsi | 7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
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| H A D | mpfs-icicle-kit-fabric.dtsi | 10 reg = <0x0 0x40000000 0x0 0xF0>;
11 microchip,sync-update-mask = /bits/ 32 <0>;
19 reg = <0x0 0x40000200 0x0 0x100>;
21 #size-cells = <0>;
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
35 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
37 bus-range = <0x0 0x7f>;
40 interrupt-map = <0 0 0 1 &pcie_intc 0>,
[all …]
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx35-pdk.dts | 15 reg = <0x80000000 0x8000000>,
16 <0x90000000 0x8000000>;
22 pinctrl-0 = <&pinctrl_esdhc1>;
30 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
31 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
32 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
33 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
34 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
35 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
41 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
[all …]
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| /linux/lib/ |
| H A D | test_min_heap.c | 39 int err = 0; in pop_verify_heap()
42 last = values[0]; in pop_verify_heap()
44 while (heap->nr > 0) { in pop_verify_heap()
46 if (last > values[0]) { in pop_verify_heap()
48 values[0]); in pop_verify_heap()
52 if (last < values[0]) { in pop_verify_heap()
54 values[0]); in pop_verify_heap()
58 last = values[0]; in pop_verify_heap()
66 int values[] = { 3, 1, 2, 4, 0x8000000, 0x7FFFFFF, 0, in test_heapify_all()
67 -3, -1, -2, -4, 0x8000000, 0x7FFFFFF }; in test_heapify_all()
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_1_1_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| H A D | smu_8_0_sh_mask.h | 27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | mvebu-mbus.txt | 65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | s3c6410-smdk6410.dts | 24 reg = <0x50000000 0x8000000>;
31 fin_pll: oscillator-0 {
35 #clock-cells = <0>;
42 #clock-cells = <0>;
49 reg = <0x18000000 0x8000000>;
54 reg = <0x18000000 0x10000>;
70 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
77 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
83 pinctrl-0 = <&uart1_data>;
89 pinctrl-0 = <&uart2_data>;
[all …]
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | rcar-pci-ep.yaml | 79 reg = <0xfe000000 0x80000>,
80 <0xfe100000 0x100000>,
81 <0xfe200000 0x200000>,
82 <0x30000000 0x8000000>,
83 <0x38000000 0x8000000>;
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| /linux/arch/mips/boot/dts/lantiq/ |
| H A D | danube.dtsi | 8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
44 reg = <0x101000 0x1000>;
49 reg = <0x102000 0x1000>;
54 reg = <0x103000 0x1000>;
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti-aemif.txt | 25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | vexpress-v2f-1xv7-ca53x2.dts | 20 arm,hbi = <0x247>;
21 arm,vexpress,site = <0xf>;
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0 0>;
54 reg = <0 1>;
67 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
75 /* Chipselect 2 is physically at 0x18000000 */
79 reg = <0 0x18000000 0 0x00800000>;
87 #address-cells = <0>;
[all …]
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| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-openblocks-ax3-4.dts | 23 memory@0 {
25 reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000
32 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
33 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
34 MBUS_ID(0x0c, 0x04) 0 0 0xd1200000 0x100000>;
44 devbus,badr-skew-ps = <0>;
47 devbus,rd-setup-ps = <0>;
[all …]
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| /linux/arch/arm/boot/dts/airoha/ |
| H A D | en7523.dtsi | 20 reg = <0x84000000 0xA00000>;
25 reg = <0x84B00000 0x100000>;
30 reg = <0x85000000 0x1A00000>;
35 reg = <0x86B00000 0x100000>;
40 reg = <0x86D00000 0x100000>;
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x1>;
91 reg = <0x1fa20000 0x400>,
[all …]
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| /linux/arch/mips/boot/dts/ralink/ |
| H A D | vocore2.dts | 9 memory@0 {
11 reg = <0x0 0x8000000>;
|
| H A D | omega2p.dts | 9 memory@0 {
11 reg = <0x0 0x8000000>;
|
| /linux/arch/arm/boot/dts/sigmastar/ |
| H A D | mstar-infinity2m-ssd202d.dtsi | 12 reg = <0x20000000 0x8000000>;
|
| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | trace-groups-table.csv | 2 INFO, 0x1
3 IRQ SVC, 0x2
4 VBIOS, 0x4
5 REGISTER, 0x8
6 PHY DBG, 0x10
7 PSR, 0x20
8 AUX, 0x40
9 SMU, 0x80
10 MALL, 0x100
11 ABM, 0x200
[all …]
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| /linux/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-a1-ad401.dts | 22 memory@0 {
24 reg = <0x0 0x0 0x0 0x8000000>;
|