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/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_reg_print.c_shipped12 { "SCSIRSTO", 0x01, 0x01 },
13 { "ENAUTOATNP", 0x02, 0x02 },
14 { "ENAUTOATNI", 0x04, 0x04 },
15 { "ENAUTOATNO", 0x08, 0x08 },
16 { "ENRSELI", 0x10, 0x10 },
17 { "ENSELI", 0x20, 0x20 },
18 { "ENSELO", 0x40, 0x40 },
19 { "TEMODE", 0x80, 0x80 }
26 0x00, regvalue, cur_col, wrap));
30 { "CLRCHN", 0x02, 0x02 },
[all …]
H A Daic7xxx_reg.h_shipped19 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
26 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
33 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
40 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
47 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
54 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
61 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
68 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
75 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
82 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
[all …]
H A Daic79xx_reg.h_shipped19 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
26 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
33 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
40 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
47 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
54 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
61 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
68 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
75 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
82 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
[all …]
H A Daic79xx_reg_print.c_shipped12 { "SPLTINT", 0x01, 0x01 },
13 { "CMDCMPLT", 0x02, 0x02 },
14 { "SEQINT", 0x04, 0x04 },
15 { "SCSIINT", 0x08, 0x08 },
16 { "PCIINT", 0x10, 0x10 },
17 { "SWTMINT", 0x20, 0x20 },
18 { "BRKADRINT", 0x40, 0x40 },
19 { "HWERRINT", 0x80, 0x80 },
20 { "INT_PEND", 0xff, 0xff }
27 0x01, regvalue, cur_col, wrap));
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.c24 #define B2055_INITTAB_ENTRY_OK 0x01
25 #define B2055_INITTAB_UPLOAD 0x02
31 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
32 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
33 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
34 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
35 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
36 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
37 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
38 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
/linux/include/linux/mfd/da9052/
H A Dreg.h14 #define DA9052_PAGE0_CON_REG 0
176 #define DA9052_PAGE_CONF 0X80
179 #define DA9052_STATUSA_VDATDET 0X80
180 #define DA9052_STATUSA_VBUSSEL 0X40
181 #define DA9052_STATUSA_DCINSEL 0X20
182 #define DA9052_STATUSA_VBUSDET 0X10
183 #define DA9052_STATUSA_DCINDET 0X08
184 #define DA9052_STATUSA_IDGND 0X04
185 #define DA9052_STATUSA_IDFLOAT 0X02
186 #define DA9052_STATUSA_NONKEY 0X01
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-samsung-s6e88a0-ams427ap24.c57 CANDELA_10CD, /* 0 */
115 /* 0 */ 10, /* 10CD */
172 { 0x03, 0x77 }, /* AOR 90.9%, 10CD */
173 { 0x03, 0x73 }, /* AOR 90.5%, 11CD */
174 { 0x03, 0x69 }, /* AOR 89.4%, 12CD */
175 { 0x03, 0x65 }, /* AOR 89.0%, 13CD */
176 { 0x03, 0x61 }, /* AOR 88.6%, 14CD */
177 { 0x03, 0x55 }, /* AOR 87.4%, 15CD */
178 { 0x03, 0x50 }, /* AOR 86.9%, 16CD */
179 { 0x03, 0x45 }, /* AOR 85.8%, 17CD */
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h13 #define SXGBE_CORE_TX_CONFIG_REG 0x0000
14 #define SXGBE_CORE_RX_CONFIG_REG 0x0004
15 #define SXGBE_CORE_PKT_FILTER_REG 0x0008
16 #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C
17 #define SXGBE_CORE_HASH_TABLE_REG0 0x0010
18 #define SXGBE_CORE_HASH_TABLE_REG1 0x0014
19 #define SXGBE_CORE_HASH_TABLE_REG2 0x0018
20 #define SXGBE_CORE_HASH_TABLE_REG3 0x001C
21 #define SXGBE_CORE_HASH_TABLE_REG4 0x0020
22 #define SXGBE_CORE_HASH_TABLE_REG5 0x0024
[all …]
/linux/arch/m68k/68000/
H A Dbootlogo.h7 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x01, 0x00, 0x00, 0x00,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9 0x00, 0x00, 0x40, 0x55, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
12 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/linux/drivers/net/ipa/reg/
H A Dgsi_reg-v3.5.1.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(15, 0),
40 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
54 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v3.1.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(15, 0),
40 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
54 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v5.0.c14 0x0000c01c + 0x1000 * GSI_EE_AP);
17 0x0000c028 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(6, 0),
29 0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
32 [CH_R_LENGTH] = GENMASK(23, 0),
37 0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
39 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
41 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
44 [WRR_WEIGHT] = GENMASK(3, 0),
56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v4.11.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(19, 0),
40 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
58 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v4.9.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(19, 0),
40 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
58 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v4.5.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(15, 0),
40 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
57 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
H A Dgsi_reg-v4.0.c14 0x0000c020 + 0x1000 * GSI_EE_AP);
17 0x0000c024 + 0x1000 * GSI_EE_AP);
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
32 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 [CH_R_LENGTH] = GENMASK(15, 0),
40 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
44 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 [WRR_WEIGHT] = GENMASK(3, 0),
55 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
[all …]
/linux/net/ncsi/
H A Dncsi-pkt.h11 unsigned char revision; /* NCSI version - 0x01 */
373 #define NCSI_PKT_REVISION 0x01
376 #define NCSI_PKT_CMD_CIS 0x00 /* Clear Initial State */
377 #define NCSI_PKT_CMD_SP 0x01 /* Select Package */
378 #define NCSI_PKT_CMD_DP 0x02 /* Deselect Package */
379 #define NCSI_PKT_CMD_EC 0x03 /* Enable Channel */
380 #define NCSI_PKT_CMD_DC 0x04 /* Disable Channel */
381 #define NCSI_PKT_CMD_RC 0x05 /* Reset Channel */
382 #define NCSI_PKT_CMD_ECNT 0x06 /* Enable Channel Network Tx */
383 #define NCSI_PKT_CMD_DCNT 0x0
[all...]
/linux/include/linux/mfd/
H A Dpalmas.h24 #define PALMAS_CHIP_OLD_ID 0x0000
25 #define PALMAS_CHIP_ID 0xC035
26 #define PALMAS_CHIP_CHARGER_ID 0xC036
43 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
133 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
135 /* Channel 0 current source can be used for battery detection.
139 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
154 * 0: reload default values from OTP on warm reset
165 * 0: i2c selection of voltage
177 * 0: Off
[all …]
/linux/drivers/net/wan/
H A Dhd64572.h4 * CPU modes 0 & 2.
15 * PC300 initial CVS version (3.4.0-pre1)
25 #define ILAR 0x00
28 #define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */
29 #define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */
30 #define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */
31 #define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */
32 #define WCRL 0x24 /* Wait Control Register L */
33 #define WCRM 0x25 /* Wait Control Register M */
34 #define WCRH 0x26 /* Wait Control Register H */
[all …]
/linux/include/linux/mfd/da9063/
H A Dregisters.h18 /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
19 /* Page 1 : SPI access 0x080 - 0x0FF */
20 /* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */
21 /* Page 3 : SPI access 0x180 - 0x1FF */
22 #define DA9063_REG_PAGE_CON 0x00
25 #define DA9063_REG_STATUS_A 0x01
26 #define DA9063_REG_STATUS_B 0x02
27 #define DA9063_REG_STATUS_C 0x03
28 #define DA9063_REG_STATUS_D 0x04
29 #define DA9063_REG_FAULT_LOG 0x05
[all …]
/linux/tools/testing/selftests/bpf/prog_tests/
H A Dsockopt_multi.c16 /* Set IP_TOS to the expected value (0x80). */ in run_getsockopt_test()
18 buf = 0x80; in run_getsockopt_test()
20 if (err < 0) { in run_getsockopt_test()
25 buf = 0x00; in run_getsockopt_test()
33 if (buf != 0x80) { in run_getsockopt_test()
34 log_err("Unexpected getsockopt 0x%x != 0x80 without BPF", buf); in run_getsockopt_test()
40 * - kernel: -> 0x80 in run_getsockopt_test()
41 * - child: 0x80 -> 0x90 in run_getsockopt_test()
49 buf = 0x00; in run_getsockopt_test()
57 if (buf != 0x90) { in run_getsockopt_test()
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml113 reg = <0 0x11000400 0 0x80>,
114 <0 0x11000480 0 0x80>,
115 <0 0x11000500 0 0x80>,
116 <0 0x11000580 0 0x80>,
117 <0 0x11000600 0 0x80>,
118 <0 0x11000680 0 0x80>,
119 <0 0x11000700 0 0x80>,
120 <0 0x11000780 0 0x80>,
121 <0 0x11000800 0 0x80>,
122 <0 0x11000880 0 0x80>,
[all …]
/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_regs.h15 #define LOGICVC_HSYNC_FRONT_PORCH_REG 0x00
16 #define LOGICVC_HSYNC_REG 0x08
17 #define LOGICVC_HSYNC_BACK_PORCH_REG 0x10
18 #define LOGICVC_HRES_REG 0x18
19 #define LOGICVC_VSYNC_FRONT_PORCH_REG 0x20
20 #define LOGICVC_VSYNC_REG 0x28
21 #define LOGICVC_VSYNC_BACK_PORCH_REG 0x30
22 #define LOGICVC_VRES_REG 0x38
24 #define LOGICVC_CTRL_REG 0x40
32 #define LOGICVC_CTRL_HSYNC_ENABLE BIT(0)
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c19 #define REG01_PMS_P_MASK GENMASK(3, 0)
23 #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
27 #define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
30 #define REG21_PMS_S_MASK GENMASK(3, 0)
60 .pixclk = 0,
61 .pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 },
68 .pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
71 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
74 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
77 .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
[all …]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]

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