| /linux/arch/powerpc/include/asm/ |
| H A D | tsi108.h | 18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
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| /linux/drivers/net/ethernet/ezchip/ |
| H A D | nps_enet.h | 10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
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| /linux/arch/mips/include/asm/sgi/ |
| H A D | hpc3.h | 22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
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| /linux/drivers/media/dvb-frontends/ |
| H A D | nxt200x.c | 33 #define CRC_CCIT_MASK 0x1021
56 #define dprintk(args...) do { if (debug) pr_debug(args); } while (0)
61 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; in i2c_writebytes()
64 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", in i2c_writebytes()
68 return 0; in i2c_writebytes()
77 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", in i2c_readbytes()
81 return 0; in i2c_readbytes()
89 …struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len +… in nxt200x_writebytes()
97 buf2[0] = reg; in nxt200x_writebytes()
101 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", in nxt200x_writebytes()
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | bmi.h | 60 BMI_NO_COMMAND = 0,
83 #define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
84 #define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000
85 #define BMI_PARAM_FLASH_SECTION_ALL 0x10000
88 #define BMI_PARAM_GET_EXT_BOARD_ID 0x40000
89 #define ATH10K_BMI_EXT_BOARD_ID_SUPPORT 0x40000
91 #define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK 0x7c00
94 #define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK 0x18000
97 #define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
98 #define ATH10K_BMI_EBOARD_ID_STATUS_MASK 0xff
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| /linux/arch/mips/rb532/ |
| H A D | irq.c | 61 .mask = 0x0000efff,
62 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
64 .mask = 0x00001fff,
67 .mask = 0x00000007,
70 .mask = 0x0003ffff,
73 .mask = 0xffffffff,
93 int ipnum = 0x100 << ip; in enable_local_irq()
100 int ipnum = 0x100 << ip; in disable_local_irq()
107 int ipnum = 0x100 << ip; in ack_local_irq()
118 if (ip < 0) in rb532_enable_irq()
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| /linux/drivers/staging/media/meson/vdec/ |
| H A D | codec_hevc_common.c | 13 #define MMU_COMPRESS_HEADER_SIZE 0x48000
14 #define MMU_MAP_SIZE 0x4800
17 0x0401, 0x8401, 0x0800, 0x0402,
18 0x9002, 0x1423, 0x8CC3, 0x1423,
19 0x8804, 0x9825, 0x0800, 0x04FE,
20 0x8406, 0x8411, 0x1800, 0x8408,
21 0x8409, 0x8C2A, 0x9C2B, 0x1C00,
22 0x840F, 0x8407, 0x8000, 0x8408,
23 0x2000, 0xA800, 0x8410, 0x04DE,
24 0x840C, 0x840D, 0xAC00, 0xA000,
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| /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
| H A D | dcore0_mme_ctrl_lo_masks.h | 24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
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| /linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
| H A D | psoc_global_conf_masks.h | 23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
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| /linux/drivers/cpufreq/ |
| H A D | sun50i-cpufreq-nvmem.c | 22 #define NVMEM_MASK 0x7
25 #define SUN50I_A100_NVMEM_MASK 0xf
48 return 0; in sun50i_h6_efuse_xlate()
59 case 0b100: in sun50i_a100_efuse_xlate()
61 case 0b010: in sun50i_a100_efuse_xlate()
64 return 0; in sun50i_a100_efuse_xlate()
79 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
80 * 0 and 2 seem identical from the OPP tables' point of view.
85 u32 value = 0; in sun50i_h616_efuse_xlate()
87 switch (speedbin & 0xffff) { in sun50i_h616_efuse_xlate()
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| /linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
| H A D | psoc_global_conf_masks.h | 23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
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| /linux/include/video/ |
| H A D | gbe.h | 20 uint32_t _pad0[0x010000/4 - 8];
29 volatile uint32_t vt_intr01; /* intr 0,1 y coords */
41 uint32_t _pad1[0xffb0/4];
42 volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */
45 uint32_t _pad2[0xfff4/4];
46 volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */
50 uint32_t _pad3[0xfff0/4];
53 uint32_t _pad4[0x7ff8/4];
55 uint32_t _pad5[0x7f80/4];
57 uint32_t _pad6[0x2000/4];
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | evergreen_reg.h | 28 #define TN_SMC_IND_INDEX_0 0x200
29 #define TN_SMC_IND_DATA_0 0x204
32 #define EVERGREEN_PIF_PHY0_INDEX 0x8
33 #define EVERGREEN_PIF_PHY0_DATA 0xc
34 #define EVERGREEN_PIF_PHY1_INDEX 0x10
35 #define EVERGREEN_PIF_PHY1_DATA 0x14
36 #define EVERGREEN_MM_INDEX_HI 0x18
38 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
39 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
40 #define EVERGREEN_D3VGA_CONTROL 0x3e0
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
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| H A D | oss_3_0_1_d.h | 27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
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| H A D | oss_3_0_d.h | 27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
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| /linux/drivers/net/ |
| H A D | sungem_phy.c | 37 { 0, 0, 0 }, /* No link */
38 { 0, 0, 0 }, /* 10BT Half Duplex */
39 { 1, 0, 0 }, /* 10BT Full Duplex */
40 { 0, 1, 0 }, /* 100BT Half Duplex */
41 { 0, 1, 0 }, /* 100BT Half Duplex */
42 { 1, 1, 0 }, /* 100BT Full Duplex*/
43 { 1, 0, 1 }, /* 1000BT */
44 { 1, 0, 1 }, /* 1000BT */
81 if ((val & BMCR_RESET) == 0) in reset_one_mii_phy()
85 if ((val & BMCR_ISOLATE) && limit > 0) in reset_one_mii_phy()
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| /linux/include/linux/mfd/ |
| H A D | motorola-cpcap.h | 17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
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| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_format_helper_test.c | 21 #define TEST_USE_DEFAULT_PITCH 0
129 .clip = DRM_RECT_INIT(0, 0, 1, 1),
130 .xrgb8888 = { 0x01FF0000 },
133 .expected = { 0x4C },
137 .expected = { 0xE0 },
141 .expected = { 0xF800 },
142 .expected_swab = { 0x00F8 },
146 .expected = { 0x7C00 },
150 .expected = { 0xFC00 },
154 .expected = { 0xF801 },
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| /linux/include/sound/ac97/ |
| H A D | regs.h | 13 #define AC97_RESET 0x00 /* Reset */
14 #define AC97_MASTER 0x02 /* Master Volume */
15 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
16 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
17 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
18 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */
19 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
20 #define AC97_MIC 0x0e /* MIC Volume */
21 #define AC97_LINE 0x10 /* Line In Volume */
22 #define AC97_CD 0x12 /* CD Volume */
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| /linux/arch/mips/include/asm/sn/sn0/ |
| H A D | hubpi.h | 24 #define PI_BASE 0x000000
28 #define PI_CPU_PROTECT 0x000000 /* CPU Protection */
29 #define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
30 #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
31 #define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */
32 #define PI_CPU_NUM 0x000020 /* CPU Number ID */
33 #define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */
34 #define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */
35 #define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */
38 #define PI_CALIAS_SIZE_0 0
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| /linux/drivers/net/ethernet/emulex/benet/ |
| H A D | be_hw.h | 19 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 #define MPU_MAILBOX_DB_OFFSET 0x160
25 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
28 #define MPU_EP_CONTROL 0
31 #define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
32 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
34 #define POST_STAGE_MASK 0x0000FFFF
35 #define POST_ERR_MASK 0x1
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| /linux/include/net/ |
| H A D | erspan.h | 6 * 0 1 2 3
7 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
9 * |0|0|0|0|0|00000|000000000|00000| Protocol Type for ERSPAN |
18 * 0 1 2 3
19 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
21 * |0|0|0|1|0|00000|000000000|00000| Protocol Type for ERSPAN |
31 * 0 1 2 3
32 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
41 * 0 1 2 3
42 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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| /linux/drivers/media/i2c/ |
| H A D | msp3400-kthreads.c | 28 { 0x0000, 0, 0, "could not detect sound standard", V4L2_STD_ALL },
29 { 0x0001, 0, 0, "autodetect start", V4L2_STD_ALL },
30 { 0x0002, MSP_CARRIER(4.5), MSP_CARRIER(4.72),
32 { 0x0003, MSP_CARRIER(5.5), MSP_CARRIER(5.7421875),
34 { 0x0004, MSP_CARRIER(6.5), MSP_CARRIER(6.2578125),
36 { 0x0005, MSP_CARRIER(6.5), MSP_CARRIER(6.7421875),
38 { 0x0006, MSP_CARRIER(6.5), MSP_CARRIER(6.5),
40 { 0x0007, MSP_CARRIER(6.5), MSP_CARRIER(5.7421875),
42 { 0x0008, MSP_CARRIER(5.5), MSP_CARRIER(5.85),
44 { 0x0009, MSP_CARRIER(6.5), MSP_CARRIER(5.85),
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| /linux/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
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