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/linux/Documentation/devicetree/bindings/sound/
H A Damlogic,g12a-tohdmitx.yaml51 reg = <0x744 0x4>;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi14 tdmif_a: audio-controller-0 {
16 #sound-dai-cells = <0>;
27 #sound-dai-cells = <0>;
38 #sound-dai-cells = <0>;
52 reg = <0x0 0x40000 0x0 0x34>;
53 #sound-dai-cells = <0>;
65 reg = <0x0 0x42000 0x0 0x2000>;
68 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
70 clkc_audio: clock-controller@0 {
73 reg = <0x0 0x0 0x0 0xb4>;
[all …]
H A Dmeson-sm1.dtsi16 tdmif_a: audio-controller-0 {
18 #sound-dai-cells = <0>;
29 #sound-dai-cells = <0>;
40 #sound-dai-cells = <0>;
50 #address-cells = <0x2>;
51 #size-cells = <0x0>;
53 cpu0: cpu@0 {
56 reg = <0x0 0x0>;
65 reg = <0x0 0x1>;
74 reg = <0x0 0x2>;
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
H A Dstm32mp13_rcc.h11 #define RCC_SECCFGR 0x0
12 #define RCC_MP_SREQSETR 0x100
13 #define RCC_MP_SREQCLRR 0x104
14 #define RCC_MP_APRSTCR 0x108
15 #define RCC_MP_APRSTSR 0x10c
16 #define RCC_PWRLPDLYCR 0x110
17 #define RCC_MP_GRSTCSETR 0x114
18 #define RCC_BR_RSTSCLRR 0x118
19 #define RCC_MP_RSTSSETR 0x11c
20 #define RCC_MP_RSTSCLRR 0x120
[all …]
/linux/drivers/memory/tegra/
H A Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
[all …]
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dregs.h2 #define A_SG_CONTROL 0x0
25 #define M_USERSPACESIZE 0x1f
29 #define M_HOSTPAGESIZE 0x7
37 #define M_PKTSHIFT 0x7
52 #define S_GLOBALENABLE 0
68 #define A_SG_KDOORBELL 0x4
74 #define S_EGRCNTX 0
75 #define M_EGRCNTX 0xffff
78 #define A_SG_GTS 0x8
81 #define M_RSPQ 0x7
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/drivers/mfd/
H A Dcs47l15-tables.c19 { 0x8C, 0x5555 },
20 { 0x8C, 0xAAAA },
21 { 0x314, 0x0080 },
22 { 0x4A8, 0x6023 },
23 { 0x4A9, 0x6023 },
24 { 0x4D4, 0x0008 },
25 { 0x4CF, 0x0F00 },
26 { 0x4D7, 0x1B2B },
27 { 0x8C, 0xCCCC },
28 { 0x8C, 0x3333 },
[all …]
H A Dcs47l35-tables.c18 { 0x460, 0x0c40 },
19 { 0x461, 0xcd1a },
20 { 0x462, 0x0c40 },
21 { 0x463, 0xb53b },
22 { 0x464, 0x0c40 },
23 { 0x465, 0x7503 },
24 { 0x466, 0x0c40 },
25 { 0x467, 0x4a41 },
26 { 0x468, 0x0041 },
27 { 0x469, 0x3491 },
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]

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