Searched +full:0 +full:x702d0000 (Results 1 – 3 of 3) sorted by relevance
84 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;100 reg = <0x702d0800 0x800>;107 ranges = <0x702d0000 0x702d0000 0x0000e400>;111 #size-cells = <0>;113 port@0 {114 reg = <0x0>;123 reg = <0xa>;132 reg = <0x702d0000 0x800>;156 #size-cells = <0>;158 admaif1_port: port@0 {[all …]
22 pattern: "^ahub@[0-9a-f]*$"70 '^port@[0-9]':75 '^i2s@[0-9a-f]+$':78 '^dmic@[0-9a-f]+$':82 '^admaif@[0-9a-f]+$':86 '^dspk@[0-9a-f]+$':90 '^mvc@[0-9a-f]+$':94 '^sfc@[0-9a-f]+$':98 '^amx@[0-9a-f]+$':102 '^adx@[0-9a-f]+$':[all …]
33 #define CLK_SOURCE_CSITE 0x1d434 #define CLK_SOURCE_EMC 0x19c35 #define CLK_SOURCE_SOR1 0x41036 #define CLK_SOURCE_SOR0 0x41437 #define CLK_SOURCE_LA 0x1f838 #define CLK_SOURCE_SDMMC2 0x15439 #define CLK_SOURCE_SDMMC4 0x16440 #define CLK_SOURCE_EMC_DLL 0x66442 #define PLLC_BASE 0x8043 #define PLLC_OUT 0x84[all …]