Searched +full:0 +full:x70040000 (Results 1 – 3 of 3) sorted by relevance
16 #define TEGRA_IRAM_BASE 0x4000000019 #define TEGRA_ARM_PERIF_BASE 0x5004000022 #define TEGRA_ARM_INT_DIST_BASE 0x5004100025 #define TEGRA_TMR1_BASE 0x6000500028 #define TEGRA_TMR2_BASE 0x6000500831 #define TEGRA_TMRUS_BASE 0x6000501034 #define TEGRA_TMR3_BASE 0x6000505037 #define TEGRA_TMR4_BASE 0x6000505840 #define TEGRA_CLK_RESET_BASE 0x6000600043 #define TEGRA_FLOW_CTRL_BASE 0x60007000[all …]
93 minimum: 0104 - 0120 # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)121 - 0135 property is missing. A value of 0 will interrupt on every OC148 default: 0153 default: 0181 const: 0244 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */245 <0x60006000 0x400>; /* CAR reg_base */[all …]
22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */31 interrupt-map-mask = <0 0 0 0>;32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;34 bus-range = <0x00 0xff>;38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */[all …]