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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml47 "^emc-timings-[0-9]+$":
56 "^timing-[0-9]+$":
118 reg = <0x70019000 0x1000>;
122 interrupts = <0 77 4>;
135 0x40040001 /* MC_EMEM_ARB_CFG */
136 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
137 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
138 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
139 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
140 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
[all …]
H A Dnvidia,tegra124-emc.yaml33 const: 0
51 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
93 minimum: 0
156 minimum: 0
356 reg = <0x70019000 0x1000>;
369 reg = <0x7001b000 0x1000>;
377 #interconnect-cells = <0>;
379 emc-timings-0 {
382 timing-0 {
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]