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Searched +full:0 +full:x70006000 (Results 1 – 10 of 10) sorted by relevance

/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/linux/arch/arm/mach-tegra/
H A Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
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/linux/Documentation/devicetree/bindings/serial/
H A Dnvidia,tegra20-hsuart.yaml72 issue. UART RX baud rate tolerance level is 0% to +4% in 1-stop config. Otherwise, the
80 As an example, consider there is deviation observed in TX for baud rates as listed below. 0
86 nvidia,adjust-baud-rates = <0 9600 100>,
116 reg = <0x70006000 0x40>;
/linux/arch/arm/include/debug/
H A Dtegra.S21 #define TEGRA_CLK_RESET_BASE 0x60006000
22 #define TEGRA_APB_MISC_BASE 0x70000000
23 #define TEGRA_UARTA_BASE 0x70006000
24 #define TEGRA_UARTB_BASE 0x70006040
25 #define TEGRA_UARTC_BASE 0x70006200
26 #define TEGRA_UARTD_BASE 0x70006300
27 #define TEGRA_UARTE_BASE 0x70006400
28 #define TEGRA_PMC_BASE 0x7000e400
30 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
31 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
[all …]
/linux/arch/m68k/include/asm/
H A Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc00>;
37 reg = <0x50000000 0x00024000>;
51 ranges = <0x54000000 0x54000000 0x04000000>;
55 reg = <0x54040000 0x00040000>;
67 reg = <0x54080000 0x00040000>;
79 reg = <0x540c0000 0x00040000>;
[all …]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0 0 0>;
36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
38 bus-range = <0x00 0xff>;
42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]