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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.yaml122 reg = <0x700008d4 0x02a8>, /* Pad control registers */
123 <0x70003000 0x1000>; /* Mux registers */
126 pinctrl-0 = <&state_boot>;
H A Dnvidia,tegra114-pinmux.yaml127 reg = <0x70000868 0x148>, /* Pad control registers */
128 <0x70003000 0x40c>; /* PinMux registers */
134 nvidia,pull = <0>;
135 nvidia,tristate = <0>;
149 nvidia,tristate = <0>;
H A Dnvidia,tegra114-pinmux.txt16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
19 until reset. 0: no, 1: yes.
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22 - nvidia,drive-type: Integer. Valid range 0...3.
98 reg = <0x70000868 0x148 /* Pad control registers */
99 0x70003000 0x40c>; /* PinMux registers */
109 nvidia,pull = <0>;
110 nvidia,tristate = <0>;
[all …]
H A Dnvidia,tegra124-pinmux.txt118 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
119 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
120 <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
152 pinctrl-0 = <&sdmmc4_default>;
H A Dnvidia,tegra30-pinmux.txt14 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
15 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
17 until reset. 0: no, 1: yes.
18 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
110 reg = < 0x70000868 0xd0 /* Pad control registers */
111 0x70003000 0x3e0 >; /* Mux registers */
122 nvidia,pull = <0>;
123 nvidia,tristate = <0>;
136 nvidia,tristate = <0>;
143 pinctrl-0 = <&sdmmc4_default>;
H A Dnvidia,tegra30-pinmux.yaml147 reg = <0x70000868 0x0d0>, /* Pad control registers */
148 <0x70003000 0x3e0>; /* Mux registers */
155 nvidia,pull = <0>;
156 nvidia,tristate = <0>;
170 nvidia,tristate = <0>;
H A Dnvidia,tegra124-pinmux.yaml147 reg = <0x70000868 0x164>, /* Pad control registers */
148 <0x70003000 0x434>, /* Mux registers */
149 <0x70000820 0x8>; /* MIPI pad control */
H A Dnvidia,tegra210-pinmux.txt29 and off/on are represented as integer values 0 and 1.
43 0: none, 1: down, 2: up.
45 0: drive, 1: tristate.
65 - nvidia,drive-type: Integer. Valid range 0...3.
66 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
69 - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
72 - nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
75 - nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
148 reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
149 <0x0 0x70003000 0x0 0x1000>; /* Mux registers */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x5000000
[all...]
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x0100380
[all...]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]