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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dnvidia,tegra20-apbmisc.yaml49 reg = <0x70000800 0x64>, /* Chip revision */
50 <0x70000008 0x04>; /* Strapping options */
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DDynamicTags.def44 DYNAMIC_TAG(NULL, 0) // Marks end of dynamic array.
91 DYNAMIC_TAG(CREL, 0x40000026) // CREL relocation table
93 DYNAMIC_TAG_MARKER(LOOS, 0x60000000) // Start of environment specific tags.
94 DYNAMIC_TAG_MARKER(HIOS, 0x6FFFFFFF) // End of environment specific tags.
95 DYNAMIC_TAG_MARKER(LOPROC, 0x70000000) // Start of processor specific tags.
96 DYNAMIC_TAG_MARKER(HIPROC, 0x7FFFFFFF) // End of processor specific tags.
100 DYNAMIC_TAG(ANDROID_REL, 0x6000000F)
101 DYNAMIC_TAG(ANDROID_RELSZ, 0x60000010)
102 DYNAMIC_TAG(ANDROID_RELA, 0x60000011)
103 DYNAMIC_TAG(ANDROID_RELASZ, 0x60000012)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x5000000
[all...]
H A Dtegra20.dtsi17 memory@0 {
19 reg = <0 0>;
24 reg = <0x40000000 0x40000>;
27 ranges = <0 0x40000000 0x40000>;
30 reg = <0x400 0x3fc0
[all...]
H A Dtegra30.dtsi20 reg = <0x80000000 0x0>;
26 reg = <0x00003000 0x00000800>, /* PADS registers */
27 <0x00003800 0x00000200>, /* AFI registers */
28 <0x10000000 0x10000000>; /* configuration space */
35 interrupt-map-mask = <0 0
[all...]
/freebsd/sys/sys/
H A Delf_common.h59 #define ODK_NULL 0 /* undefined */
75 #define OEX_FPU_MIN 0x0000001f /* min FPU exception required */
76 #define OEX_FPU_MAX 0x00001f00 /* max FPU exception allowed */
77 #define OEX_PAGE0 0x00010000 /* page zero must be mapped */
78 #define OEX_SMM 0x00020000 /* run in sequential memory mode */
79 #define OEX_PRECISEFP 0x00040000 /* run in precise FP exception mode */
80 #define OEX_DISMISS 0x00080000 /* dismiss invalid address traps */
85 #define OPAD_PREFIX 0x0001
86 #define OPAD_POSTFIX 0x0002
87 #define OPAD_SYMBOL 0x0004
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]