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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv04.c51 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
59 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
78 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
137 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new()
149 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
155 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
197 return 0; in nv04_instmem_suspend()
210 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
214 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
215 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
[all …]
H A Dnv50.c62 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; in nv50_instobj_wr32_slow()
63 u64 addr = (nvkm_memory_addr(iobj->ram) + offset) & 0x000000fffffULL; in nv50_instobj_wr32_slow()
68 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_wr32_slow()
71 nvkm_wr32(device, 0x700000 + addr, data); in nv50_instobj_wr32_slow()
81 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; in nv50_instobj_rd32_slow()
82 u64 addr = (nvkm_memory_addr(iobj->ram) + offset) & 0x000000fffffULL; in nv50_instobj_rd32_slow()
88 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_rd32_slow()
91 data = nvkm_rd32(device, 0x700000 + addr); in nv50_instobj_rd32_slow()
162 if (ret == 0) in nv50_instobj_kmap()
163 ret = nvkm_memory_map(memory, 0, vmm, bar, NULL, 0); in nv50_instobj_kmap()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs8550.dtsi40 * 0x80000000 +-------------------+
44 * 0x8a800000 +-------------------+
48 * 0xa7000000 +-------------------+
52 * 0xd4d00000 +-------------------+
56 * 0x100000000 +-------------------+
60 reg = <0x0 0x81c00000 0x0 0x60000>;
66 reg = <0x0 0x81c60000 0x0 0x20000>;
72 reg = <0x0 0x81c80000 0x0 0x20000>;
77 reg = <0x0 0x81d00000 0x0 0x200000>;
83 reg = <0x0 0x81f00000 0x0 0x20000>;
[all …]
H A Dmsm8994-huawei-angler-rev-101.dts17 qcom,msm-id = <207 0x20000>;
18 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
19 qcom,board-id = <8026 0>;
35 reg = <0 0x03401000 0 0x1000000>;
40 reg = <0 0x04800000 0 0x1900000>;
45 reg = <0 0x06300000 0 0x700000>;
54 pinctrl-0 = <&blsp1_uart2_default>;
/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dti,j721e-esm.yaml50 reg = <0x0 0x700000 0x0 0x1000>;
/linux/arch/arm/mach-davinci/
H A Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a.dtsi33 /* MC34VR500 DC/DC regulator at 0x8, managed by PMIC */
34 /* On-board PMC at 0x11 */
38 reg = <0x4c>;
44 reg = <0x51>;
50 reg = <0x54>;
59 reg = <0x8>;
67 qflash0: flash@0 {
74 reg = <0>;
81 uboot@0 {
83 reg = <0x0 0xe0000>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226-samsung-matisse-common.dtsi29 reg = <0x03200000 0x800000>;
82 pinctrl-0 = <&backlight_i2c_default_state>;
88 #size-cells = <0>;
92 reg = <0x2c>;
94 dev-ctrl = /bits/ 8 <0x80>;
95 init-brt = /bits/ 8 <0x3f>;
97 pwms = <&backlight_pwm 0 100000>;
101 rom-addr = /bits/ 8 <0xa0>;
102 rom-val = /bits/ 8 <0x44>;
106 rom-addr = /bits/ 8 <0xa1>;
[all …]
H A Dqcom-apq8026-samsung-milletwifi.dts37 reg = <0x03200000 0x800000>;
90 pinctrl-0 = <&backlight_i2c_default_state>;
96 #size-cells = <0>;
100 reg = <0x2c>;
103 dev-ctrl = /bits/ 8 <0x80>;
104 init-brt = /bits/ 8 <0x3f>;
112 rom-addr = /bits/ 8 <0xa3>;
113 rom-val = /bits/ 8 <0x5e>;
118 * (0, 120deg, 240deg, -, -, -),
122 rom-addr = /bits/ 8 <0xa5>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]
/linux/arch/m68k/coldfire/
H A Dstmark2.c25 .size = 0x100000,
26 .offset = 0x0
29 .size = 0x700000,
49 .bus_num = 0,
56 /* SPI controller data, SPI (0) */
59 .bus_num = 0,
65 [0] = {
67 .end = MCFDSPI_BASE0 + 0xFF,
87 .id = 0,
107 __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); in init_stmark2()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sc8180x-tlmm.yaml61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
108 reg = <0x03100000 0x300000>,
109 <0x03500000 0x700000>,
110 <0x03d00000 0x300000>;
117 gpio-ranges = <&tlmm 0 0 190>;
/linux/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dshadowramin.c35 if (offset + length <= 0x00100000) { in pramin_read()
37 *(u32 *)&bios->data[i] = nvkm_rd32(device, 0x700000 + i); in pramin_read()
40 return 0; in pramin_read()
49 nvkm_wr32(device, 0x001700, priv->bar0); in pramin_fini()
60 u64 addr = 0; in pramin_init()
68 addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */ in pramin_init()
71 addr = nvkm_rd32(device, 0x021c04); in pramin_init()
74 addr = nvkm_rd32(device, 0x022500); in pramin_init()
75 if (addr & 0x00000001) { in pramin_init()
85 addr = nvkm_rd32(device, 0x625f04); in pramin_init()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Delmer0.h39 #define A_ELMER0_VERSION 0x100000
40 #define A_ELMER0_PHY_CFG 0x100004
41 #define A_ELMER0_INT_ENABLE 0x100008
42 #define A_ELMER0_INT_CAUSE 0x10000c
43 #define A_ELMER0_GPI_CFG 0x100010
44 #define A_ELMER0_GPI_STAT 0x100014
45 #define A_ELMER0_GPO 0x100018
46 #define A_ELMER0_PORT0_MI1_CFG 0x400000
48 #define S_MI1_MDI_ENABLE 0
61 #define M_MI1_SOF 0x3
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi17 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
18 <0x00000008 0x80000000 0x00000000 0x80000000>;
27 reg = <0x00 0x9e800000 0x00 0x01800000>;
28 alignment = <0x1000>;
34 reg = <0x00 0xa0000000 0x00 0x100000>;
40 reg = <0x00 0xa0100000 0x00 0xf00000>;
46 reg = <0x00 0xa1000000 0x00 0x100000>;
52 reg = <0x00 0xa1100000 0x00 0xf00000>;
58 reg = <0x00 0xa2000000 0x00 0x100000>;
64 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/linux/drivers/video/fbdev/
H A Dg364fb.c34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
[all …]

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