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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv04.c51 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
59 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
78 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
137 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new()
149 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
155 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
197 return 0; in nv04_instmem_suspend()
210 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
214 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
215 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dti,j721e-esm.yaml50 reg = <0x0 0x700000 0x0 0x1000>;
/linux/arch/arm/mach-davinci/
H A Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226-samsung-matisse-common.dtsi35 reg = <0x03200000 0x800000>;
88 pinctrl-0 = <&backlight_i2c_default_state>;
94 #size-cells = <0>;
98 reg = <0x2c>;
100 dev-ctrl = /bits/ 8 <0x80>;
101 init-brt = /bits/ 8 <0x3f>;
103 pwms = <&backlight_pwm 0 100000>;
107 rom-addr = /bits/ 8 <0xa0>;
108 rom-val = /bits/ 8 <0x44>;
112 rom-addr = /bits/ 8 <0xa1>;
[all …]
H A Dqcom-apq8026-samsung-milletwifi.dts39 reg = <0x03200000 0x800000>;
92 pinctrl-0 = <&backlight_i2c_default_state>;
98 #size-cells = <0>;
102 reg = <0x2c>;
105 dev-ctrl = /bits/ 8 <0x80>;
106 init-brt = /bits/ 8 <0x3f>;
114 rom-addr = /bits/ 8 <0xa3>;
115 rom-val = /bits/ 8 <0x5e>;
120 * (0, 120deg, 240deg, -, -, -),
124 rom-addr = /bits/ 8 <0xa5>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sc8180x-tlmm.yaml61 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
108 reg = <0x03100000 0x300000>,
109 <0x03500000 0x700000>,
110 <0x03d00000 0x300000>;
117 gpio-ranges = <&tlmm 0 0 190>;
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Delmer0.h39 #define A_ELMER0_VERSION 0x100000
40 #define A_ELMER0_PHY_CFG 0x100004
41 #define A_ELMER0_INT_ENABLE 0x100008
42 #define A_ELMER0_INT_CAUSE 0x10000c
43 #define A_ELMER0_GPI_CFG 0x100010
44 #define A_ELMER0_GPI_STAT 0x100014
45 #define A_ELMER0_GPO 0x100018
46 #define A_ELMER0_PORT0_MI1_CFG 0x400000
48 #define S_MI1_MDI_ENABLE 0
61 #define M_MI1_SOF 0x3
[all …]
/linux/drivers/video/fbdev/
H A Dg364fb.c34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-dlink-dns327l.dts9 * There's still some unknown device on i2c address 0x13
28 memory@0 {
30 reg = <0x00000000 0x20000000>; /* 512 MiB */
34 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
35 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
36 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
52 pinctrl-0 = <
73 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
79 pinctrl-0 = <
110 pinctrl-0 = <&xhci_pwr_pin>;
[all …]
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-vf610.c16 VF610_PAD_PTA6 = 0,
307 reg &= ~0x2; in vf610_pmx_gpio_set_direction()
309 reg |= 0x2; in vf610_pmx_gpio_set_direction()
312 return 0; in vf610_pmx_gpio_set_direction()
320 .mux_mask = 0x700000,
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953-xiaomi-tissot.dts21 qcom,msm-id = <293 0>;
22 qcom,board-id = <0x1000b 0x00>;
28 pinctrl-0 = <&gpio_key_default>, <&gpio_hall_sensor_default>;
47 reg = <0x0 0x84a00000 0x0 0x1900000>;
52 reg = <0x0 0x8d600000 0x0 0x1200000>;
57 reg = <0x0 0x8e800000 0x0 0x700000>;
63 reg = <0x0 0x9ff00000 0x0 0x00100000>;
64 record-size = <0x1000>;
65 console-size = <0x80000>;
66 ftrace-size = <0x1000>;
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm750-evb.dts50 reg = <0x0 0x20000000>;
70 flash@0 {
75 reg = <0>;
81 bbuboot1@0 {
83 reg = <0x0000000 0x80000>;
88 reg = <0x0080000 0x80000>;
93 reg = <0x0100000 0x40000>;
98 reg = <0x0140000 0xC0000>;
102 reg = <0x0200000 0x400000>;
106 reg = <0x0600000 0x700000>;
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/linux/arch/arm/nwfpe/
H A Dfpa11_cprt.c26 if (opcode & 0x800000) { in EmulateCPRT()
35 switch ((opcode & 0x700000) >> 20) { in EmulateCPRT()
51 return 0; in EmulateCPRT()
64 roundData.exception = 0; in PerformFLT()
91 return 0; in PerformFLT()
108 roundData.exception = 0; in PerformFIX()
132 return 0; in PerformFIX()
146 int e_flag = opcode & 0x400000; /* 1 if CxFE */ in PerformComparison()
147 int n_flag = opcode & 0x200000; /* 1 if CNxx */ in PerformComparison()
148 unsigned int flags = 0; in PerformComparison()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp.dtsi59 #size-cells = <0>;
62 A35_0: cpu@0 {
65 reg = <0x0 0x0>;
67 i-cache-size = <0x8000>;
70 d-cache-size = <0x8000>;
82 reg = <0x0 0x1>;
84 i-cache-size = <0x8000>;
87 d-cache-size = <0x8000>;
99 reg = <0x0 0x2>;
101 i-cache-size = <0x8000>;
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dreg.h7 #define TXPKT_BUF_SELECT 0x69
8 #define RXPKT_BUF_SELECT 0xA5
9 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
11 #define REG_SYS_ISO_CTRL 0x0000
12 #define REG_SYS_FUNC_EN 0x0002
13 #define REG_APS_FSMCO 0x0004
14 #define REG_SYS_CLKR 0x0008
15 #define REG_9346CR 0x000A
16 #define REG_EE_VPD 0x000C
17 #define REG_SYS_SWR_CTRL1 0x0010
[all …]

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