/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | mme1_rtr_masks.h | 23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0 24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7 26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700 28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000 30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000 33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0 34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7 36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700 38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000 40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000 [all …]
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H A D | pci_nrtr_masks.h | 23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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H A D | tpc0_nrtr_masks.h | 23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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H A D | dma_nrtr_masks.h | 23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_4_2_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
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H A D | uvd_3_1_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
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H A D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
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H A D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
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/linux/include/dt-bindings/clock/ |
H A D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100 14 #define CLK_APB3_I2C1 0x108 15 #define CLK_APB3_DAC 0x110 16 #define CLK_APB3_ADC0 0x118 17 #define CLK_APB3_ADC1 0x120 18 #define CLK_APB3_CAN0 0x128 19 #define CLK_APB1_BUS 0x200 20 #define CLK_APB1_MOTOCON_PWM 0x208 21 #define CLK_APB1_I2C0 0x210 22 #define CLK_APB1_I2S 0x218 [all …]
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/linux/arch/sh/include/cpu-sh4a/cpu/ |
H A D | dma.h | 9 #define DMTE0_IRQ evt2irq(0x800) 10 #define DMTE4_IRQ evt2irq(0xb80) 11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 12 #define SH_DMAC_BASE0 0xFE008020 14 #define DMTE0_IRQ evt2irq(0x800) 15 #define DMTE4_IRQ evt2irq(0xb80) 16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 17 #define SH_DMAC_BASE0 0xFE008020 19 #define DMTE0_IRQ evt2irq(0x640) 20 #define DMTE4_IRQ evt2irq(0x780) [all …]
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/linux/arch/loongarch/include/asm/ |
H A D | barrier.h | 11 * Bit4: ordering or completion (0: completion, 1: ordering) 12 * Bit3: barrier for previous read (0: true, 1: false) 13 * Bit2: barrier for previous write (0: true, 1: false) 14 * Bit1: barrier for succeeding read (0: true, 1: false) 15 * Bit0: barrier for succeeding write (0: true, 1: false) 17 * Hint 0x700: barrier for "read after read" from the same address 20 #define DBAR(hint) __asm__ __volatile__("dbar %0 " : : "I"(hint) : "memory") 22 #define crwrw 0b00000 23 #define cr_r_ 0b00101 24 #define c_w_w 0b01010 [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | renesas,usb2-phy.yaml | 67 enum: [0, 1] # and 0 is deprecated. 150 reg = <0xee080200 0x700>; 158 reg = <0xee0a0200 0x700>;
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/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_2_4_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff 28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 29 #define IH_VMID_1_LUT__PASID_MASK 0xffff 30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_2_LUT__PASID_MASK 0xffff 32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_3_LUT__PASID_MASK 0xffff 34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 35 #define IH_VMID_4_LUT__PASID_MASK 0xffff 36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 [all …]
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H A D | oss_2_0_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff 28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 29 #define IH_VMID_1_LUT__PASID_MASK 0xffff 30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_2_LUT__PASID_MASK 0xffff 32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 33 #define IH_VMID_3_LUT__PASID_MASK 0xffff 34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 35 #define IH_VMID_4_LUT__PASID_MASK 0xffff 36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 [all …]
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/linux/arch/x86/include/asm/ |
H A D | apicdef.h | 14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 23 #define APIC_DELIVERY_MODE_FIXED 0 30 #define APIC_ID 0x20 32 #define APIC_LVR 0x30 33 #define APIC_LVR_MASK 0xFF00FF 35 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 38 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 42 #define APIC_XAPIC(x) ((x) >= 0x14) [all …]
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/linux/include/linux/ |
H A D | cb710.h | 109 #define cb710_dump_regs(c, d) do {} while (0) 112 #define CB710_DUMP_REGS_MMC 0x0F 113 #define CB710_DUMP_REGS_MS 0x30 114 #define CB710_DUMP_REGS_SM 0xC0 115 #define CB710_DUMP_REGS_ALL 0xFF 116 #define CB710_DUMP_REGS_MASK 0xFF 118 #define CB710_DUMP_ACCESS_8 0x100 119 #define CB710_DUMP_ACCESS_16 0x200 120 #define CB710_DUMP_ACCESS_32 0x400 121 #define CB710_DUMP_ACCESS_ALL 0x700 [all …]
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/linux/drivers/regulator/ |
H A D | mt6358-regulator.c | 54 .enable_mask = BIT(0), \ 58 .qi = BIT(0), \ 82 .vsel_mask = GENMASK(3, 0), \ 107 .enable_mask = BIT(0), \ 112 .qi = BIT(0), \ 127 .vsel_mask = GENMASK(3, 0), \ 155 .enable_mask = BIT(0), \ 159 .qi = BIT(0), \ 183 .vsel_mask = GENMASK(3, 0), \ 208 .enable_mask = BIT(0), \ [all …]
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H A D | mt6357-regulator.c | 53 .enable_mask = BIT(0), \ 75 .enable_mask = BIT(0), \ 96 .enable_mask = BIT(0), \ 99 .da_vsel_mask = 0x7f00, \ 114 .enable_mask = BIT(0), \ 134 if (ret != 0) { in mt6357_get_buck_voltage_sel() 178 0, 186 0, 188 0, 189 0, [all …]
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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | psoc_etr_masks.h | 24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF 28 #define PSOC_ETR_STS_FULL_SHIFT 0 29 #define PSOC_ETR_STS_FULL_MASK 0x1 31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2 33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4 35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8 37 #define PSOC_ETR_STS_EMPTY_MASK 0x10 39 #define PSOC_ETR_STS_MEMERR_MASK 0x20 42 #define PSOC_ETR_RRD_RRD_SHIFT 0 [all …]
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/linux/tools/perf/arch/powerpc/util/ |
H A D | book3s_hv_exits.h | 10 {0x0, "RETURN_TO_HOST"}, \ 11 {0x100, "SYSTEM_RESET"}, \ 12 {0x200, "MACHINE_CHECK"}, \ 13 {0x300, "DATA_STORAGE"}, \ 14 {0x380, "DATA_SEGMENT"}, \ 15 {0x400, "INST_STORAGE"}, \ 16 {0x480, "INST_SEGMENT"}, \ 17 {0x500, "EXTERNAL"}, \ 18 {0x502, "EXTERNAL_HV"}, \ 19 {0x600, "ALIGNMENT"}, \ [all …]
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/linux/arch/powerpc/kvm/ |
H A D | trace_book3s.h | 10 {0x100, "SYSTEM_RESET"}, \ 11 {0x200, "MACHINE_CHECK"}, \ 12 {0x300, "DATA_STORAGE"}, \ 13 {0x380, "DATA_SEGMENT"}, \ 14 {0x400, "INST_STORAGE"}, \ 15 {0x480, "INST_SEGMENT"}, \ 16 {0x500, "EXTERNAL"}, \ 17 {0x502, "EXTERNAL_HV"}, \ 18 {0x600, "ALIGNMENT"}, \ 19 {0x700, "PROGRAM"}, \ [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_4_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
H A D | fsl,qe-si.yaml | 39 reg = <0x700 0x80>;
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/linux/drivers/bus/ |
H A D | omap_l3_noc.h | 16 #define CUSTOM_ERROR 0x2 17 #define STANDARD_ERROR 0x0 18 #define INBAND_ERROR 0x0 19 #define L3_APPLICATION_ERROR 0x0 20 #define L3_DEBUG_ERROR 0x1 23 #define L3_TARG_STDERRLOG_MAIN 0x48 24 #define L3_TARG_STDERRLOG_HDR 0x4c 25 #define L3_TARG_STDERRLOG_MSTADDR 0x50 26 #define L3_TARG_STDERRLOG_INFO 0x58 27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c [all …]
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/linux/drivers/pci/controller/dwc/ |
H A D | pcie-rcar-gen4.c | 27 /* PCIe Mode Setting Register 0 */ 28 #define PCIEMSR0 0x0000 30 #define DEVICE_TYPE_EP 0 32 #define BIFUR_MOD_SET_ON BIT(0) 34 /* PCIe Interrupt Status 0 */ 35 #define PCIEINTSTS0 0x0084 37 /* PCIe Interrupt Status 0 Enable */ 38 #define PCIEINTSTS0EN 0x0310 44 #define PCIEDMAINTSTSEN 0x0314 45 #define PCIEDMAINTSTSEN_INIT GENMASK(15, 0) [all …]
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