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Searched +full:0 +full:x68000 (Results 1 – 24 of 24) sorted by relevance

/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_regs.h22 #define mmMME0_QM_GLBL_CFG0 0x68000
24 #define mmMME0_QM_GLBL_CFG1 0x68004
26 #define mmMME0_QM_GLBL_PROT 0x68008
28 #define mmMME0_QM_GLBL_ERR_CFG 0x6800C
30 #define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
32 #define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
34 #define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
36 #define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
38 #define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
40 #define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_color_regs.h12 #define _PALETTE_A 0xa000
13 #define _PALETTE_B 0xa800
14 #define _CHV_PALETTE_C 0xc000
18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
32 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
40 #define _PIPEAGCMAX 0x70010
41 #define _PIPEBGCMAX 0x71010
45 #define _LGC_PALETTE_A 0x4a000
46 #define _LGC_PALETTE_B 0x4a800
[all …]
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
[all …]
/linux/drivers/parisc/
H A Dsuperio.c32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
54 * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
55 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
100 outb (OCW3_POLL,IC_PIC1+0); in superio_interrupt()
102 results = inb(IC_PIC1+0); in superio_interrupt()
105 * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending in superio_interrupt()
107 * Bits 2-0: highest priority, active requesting interrupt ID (0-7) in superio_interrupt()
109 if ((results & 0x80) == 0) { in superio_interrupt()
118 local_irq = results & 0x0f; in superio_interrupt()
129 outb(OCW3_ISR,IC_PIC1+0); in superio_interrupt()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
66 #clock-cells = <0>;
89 #address-cells = <0>;
91 reg = <0x0 0xfff01000 0 0x1000>,
92 <0x0 0xfff02000 0 0x2000>,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_4_1_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_3_0_2_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_3_3_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_3_0_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_2_0_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_3_0_1_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_9_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_9_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_1_7_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA18},
26 {0xA84, 0xA94},
27 {0xAA8, 0xAD4},
28 {0xADC, 0xB40},
29 {0x1000, 0x10A4},
30 {0x10BC, 0x111C},
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx75.c67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
20 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
21 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
22 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
23 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
24 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
25 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
26 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
27 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]