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/freebsd/sys/crypto/des/arch/i386/
H A Ddes_enc.S85 andl $0xf0f0f0f0, %eax
92 andl $0xfff0000f, %edi
99 andl $0x33333333, %eax
106 andl $0x03fc03fc, %esi
113 andl $0xaaaaaaaa, %eax
120 cmpl $0, %ebx
123 /* Round 0 */
129 andl $0xfcfcfcfc, %eax
130 andl $0xcfcfcfcf, %edx
137 movl 0x200+_C_LABEL(des_SPtrans)(%ecx),%ebp
[all …]
/freebsd/sys/crypto/openssl/i386/
H A Dcrypt586.S52 andl $0xfcfcfcfc,%eax
54 andl $0xcfcfcfcf,%edx
62 xorl 0x200(%ebp,%ecx,1),%edi
65 xorl 0x100(%ebp,%ebx,1),%edi
68 xorl 0x300(%ebp,%ecx,1),%edi
70 andl $0xff,%eax
71 andl $0xff,%edx
72 movl 0x600(%ebp,%ebx,1),%ebx
74 movl 0x700(%ebp,%ecx,1),%ebx
76 movl 0x400(%ebp,%eax,1),%ebx
[all …]
H A Ddes-586.S21 andl $0xfcfcfcfc,%eax
22 andl $0xcfcfcfcf,%edx
28 xorl 0x200(%ebp,%ecx,1),%edi
31 xorl 0x100(%ebp,%ebx,1),%edi
34 xorl 0x300(%ebp,%ecx,1),%edi
36 andl $0xff,%eax
37 andl $0xff,%edx
38 xorl 0x600(%ebp,%ebx,1),%edi
39 xorl 0x700(%ebp,%ecx,1),%edi
41 xorl 0x400(%ebp,%eax,1),%edi
[all …]
/freebsd/sys/dev/drm2/
H A Ddrm_edid_modes.h36 736, 832, 0, 350, 382, 385, 445, 0,
40 736, 832, 0, 400, 401, 404, 445, 0,
44 828, 936, 0, 400, 401, 404, 446, 0,
48 752, 800, 0, 480, 489, 492, 525, 0,
52 704, 832, 0, 480, 489, 492, 520, 0,
56 720, 840, 0, 480, 481, 484, 500, 0,
60 752, 832, 0, 480, 481, 484, 509, 0,
62 /* 800x600@56Hz */
63 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
64 896, 1024, 0, 600, 601, 603, 625, 0,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm63148.dtsi18 #size-cells = <0>;
20 B15_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0 0x80030000 0x8000>;
87 reg = <0x1000 0x1000>,
88 <0x2000 0x2000>,
89 <0x4000 0x2000>,
[all …]
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Dbcm6846.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
82 ranges = <0 0x81000000 0x8000>;
89 reg = <0x1000 0x1000>,
90 <0x2000 0x2000>,
91 <0x4000 0x2000>,
[all …]
H A Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
H A Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
H A Dbcm63178.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
100 ranges = <0 0x81000000 0x8000>;
107 reg = <0x1000 0x1000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
H A Dlan966x.dtsi27 #size-cells = <0>;
29 cpu@0 {
33 reg = <0x0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
90 reg = <0x00200000 0x80000>,
91 <0xe0808000 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8998.dtsi16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dipq9574.dtsi24 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #size-cells = <0>;
37 CPU0: cpu@0 {
40 reg = <0x0>;
53 reg = <0x1>;
66 reg = <0x2>;
79 reg = <0x3>;
99 qcom,dload-mode = <&tcsr 0x6100>;
106 reg = <0x0 0x40000000 0x0 0x0>;
[all …]
H A Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
H A Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_spi_var.h122 0, 0x600, BUS_SPACE_BARRIER_WRITE)
124 0, 0x600, BUS_SPACE_BARRIER_READ)
126 0, 0x600, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Datmel-hsmci.txt26 reg = <0xf0008000 0x600>;
29 #size-cells = <0>;
49 slot@0 {
50 reg = <0>;
52 cd-gpios = <&pioD 15 0>
59 reg = <0xf0008000 0x600>;
62 #size-cells = <0>;
63 slot@0 {
64 reg = <0>;
66 cd-gpios = <&pioD 15 0>
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
14 number on the specific port (between 0 and 31).
21 0 - Primary function
28 0 - Input
37 0 - A_IN
46 0 - GPIO_IN
52 CONFIG can be 0 or 1, meaning Pullup disable/enable.
64 reg = <0x10015000 0x600>;
78 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
79 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
[all …]
/freebsd/sys/sys/
H A Dfbio.h55 #define FBTYPE_SUN1BW 0 /* multibus mono */
105 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
171 return (0); in register_framebuffer()
179 return (0); in unregister_framebuffer()
187 int index; /* first element (0 origin) */
202 #define V_INFO_COLOR (1 << 0)
221 #define V_INFO_MM_TEXT 0
244 #define KD_OTHER 0 /* unknown */
256 #define V_ADP_COLOR (1 << 0)
332 #define V_ADP_PRIMARY 0
[all …]
/freebsd/sys/dev/videomode/
H A Dedidreg.h37 #define EDID_OFFSET_SIGNATURE 0x00
38 #define EDID_OFFSET_MANUFACTURER_ID 0x08
39 #define EDID_OFFSET_PRODUCT_ID 0x0a
40 #define EDID_OFFSET_SERIAL_NUMBER 0x0c
41 #define EDID_OFFSET_MANUFACTURE_WEEK 0x10
42 #define EDID_OFFSET_MANUFACTURE_YEAR 0x11
43 #define EDID_OFFSET_VERSION 0x12
44 #define EDID_OFFSET_REVISION 0x13
45 #define EDID_OFFSET_VIDEO_INPUT 0x14
46 #define EDID_OFFSET_MAX_HSIZE 0x15 /* in cm */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcmbca/
H A Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
H A Dbcm63146.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
75 #clock-cells = <0>;
89 ranges = <0x0 0x0 0x81000000 0x8000>;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]

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