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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra-ccplex-cluster.yaml21 pattern: "ccplex@([0-9a-f]+)$"
48 reg = <0x0e000000 0x5ffff>;
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc_regs.h12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
14 #define _PIPEDMC_CONTROL_A 0x45250
15 #define _PIPEDMC_CONTROL_B 0x45254
19 #define PIPEDMC_ENABLE REG_BIT(0)
21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)
24 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000
25 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000
30 0x400 * ((dmc_id) - 1))
32 #define __DMC_REG_MMIO_BASE 0x8f000
43 #define _DMC_EVT_HTP_0 0x8f004
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]