Searched +full:0 +full:x5f000 (Results 1 – 5 of 5) sorted by relevance
12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC014 #define _PIPEDMC_CONTROL_A 0x4525015 #define _PIPEDMC_CONTROL_B 0x4525419 #define PIPEDMC_ENABLE REG_BIT(0)21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250)24 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f00025 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x9200030 0x400 * ((dmc_id) - 1))32 #define __DMC_REG_MMIO_BASE 0x8f00043 #define _DMC_EVT_HTP_0 0x8f004[all …]
28 const: 049 reg = <0x5f000 0x800>;51 #phy-cells = <0>;56 reg = <0x5f800 0x800>;
35 reg = <0 0x4000000 0 0x200000>;40 reg = <0 0x4400000 0 0x1000000>;47 #size-cells = <0>;48 cpu0: cpu@0 {51 reg = <0>;85 /* 32M internal register @ 0xd000_0000 */86 ranges = <0x0 0x0 0xd0000000 0x2000000>;90 reg = <0x8300 0x40>;98 reg = <0xd000 0x1000>;104 #size-cells = <0>;[all …]
21 #define DEBUG_LEVEL_1_BIT (0x0001)22 #define DEBUG_LEVEL_2_BIT (0x0002)23 #define DEBUG_LEVEL_3_BIT (0x0004)24 #define DEBUG_LEVEL_4_BIT (0x0008)25 #define DEBUG_TIMING_BIT (0x1000)28 #define DEBUG 0x000156 } while (0)66 } while (0)69 asm volatile(" rd %%tick, %0\n" : "=r" (_x))94 .name = "read", .total = 0, .count = 0, .bytes = 0};[all …]
13 DBG_NONE = 0,14 DBG_INIT = BIT(0), /* driver init */26 DBG_ALL = ~0,36 } while (0)53 #define DEFAULT_HOPCOUNT 0xff54 #define DEFAULT_DESTID 0xff57 #define PCI_DEVICE_ID_TSI721 0x80ab59 #define BAR_0 067 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */[all …]