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Searched +full:0 +full:x5c000 (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3576-cru.yaml53 reg = <0xfd7c0000 0x5c000>;
H A Drockchip,rk3588-cru.yaml64 reg = <0xfd7c0000 0x5c000>;
/linux/drivers/gpu/drm/amd/include/asic_reg/clk/
H A Dclk_11_5_0_offset.h26 // base address: 0x5c000
27 …CLK1_0_CLK1_CLK_PLL_REQ 0x0410
28 …ne mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX 0
29 …CLK1_0_CLK1_CLK0_BYPASS_CNTL 0x044a
30 …ne mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX 0
31 …CLK1_0_CLK1_CLK1_BYPASS_CNTL 0x0454
32 …ne mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX 0
33 …CLK1_0_CLK1_CLK2_BYPASS_CNTL 0x045e
34 …ne mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX 0
35 …CLK1_0_CLK1_CLK3_DS_CNTL 0x0461
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,comphy-cp110.yaml32 - description: Lane 0 (USB3/GbE) registers (Armada 3700)
47 const: 0
62 '^phy@[0-5]$':
121 reg = <0x120000 0x6000>;
125 #size-cells = <0>;
128 phy@0 {
129 reg = <0>;
142 reg = <0x18300 0x300>,
143 <0x1F000 0x400>,
144 <0x5C000 0x400>,
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7.dtsi19 #address-cells = <0x2>;
20 #size-cells = <0x0>;
57 reg = <0x0 0x100>;
60 d-cache-size = <0x8000>;
63 i-cache-size = <0x8000>;
71 reg = <0x0 0x101>;
74 d-cache-size = <0x8000>;
77 i-cache-size = <0x8000>;
85 reg = <0x0 0x102>;
88 d-cache-size = <0x8000>;
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-qcs8300.c59 .offset = 0x0,
62 .enable_reg = 0x4b028,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
98 .offset = 0x1000,
101 .enable_reg = 0x4b028,
115 .offset = 0x4000,
118 .enable_reg = 0x4b028,
132 .offset = 0x7000,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-sa8775p.c73 .offset = 0x0,
76 .enable_reg = 0x4b028,
77 .enable_mask = BIT(0),
88 { 0x1, 2 },
93 .offset = 0x0,
110 .offset = 0x1000,
113 .enable_reg = 0x4b028,
125 .offset = 0x4000,
128 .enable_reg = 0x4b028,
140 .offset = 0x5000,
[all …]