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/linux/Documentation/devicetree/bindings/pci/
H A Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/linux/arch/arm/mach-pxa/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/linux/arch/arm/mach-omap2/
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-img.dtsi8 #clock-cells = <0>;
15 #clock-cells = <0>;
24 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
27 reg = <0x58100000 0x80000>;
60 reg = <0x58220000 0x1000>;
68 fsl,channel = <0>;
74 reg = <0x58222000 0x1000>;
77 interrupts = <0>;
86 reg = <0x58223018 0x4>;
96 reg = <0x5822301c 0x4>;
[all …]
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap-dss.txt50 reg = <0x58000000 0x80>;
61 reg = <0x58001000 0x1000>;
70 reg = <0x58006000 0x200>,
71 <0x58006200 0x100>,
72 <0x58006300 0x100>,
73 <0x58006400 0x1000>;
99 tfp410: encoder@0 {
101 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */
104 pinctrl-0 = <&tfp410_pins>;
108 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f4-s4sk.dts38 reg = <0x0 0x48000000 0x0 0x58000000>;
43 reg = <0x4 0x80000000 0x0 0x80000000>;
69 pinctrl-0 = <&hscif0_pins>;
78 pinctrl-0 = <&hscif1_pins>;
86 pinctrl-0 = <&i2c2_pins>;
94 pinctrl-0 = <&i2c4_pins>;
102 pinctrl-0 = <&i2c5_pins>;
110 reg = <0x50>;
116 pinctrl-0 = <&sd_pins>;
126 pinctrl-0 = <&scif_clk_pins>;
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
H A Ddra7.dtsi60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
118 opp-supported-hw = <0xFF 0x02>;
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dpci.c15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7927),
21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x6639),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0738),
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7928),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7935),
73 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
78 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
119 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail_device.c32 return 0; in oaktrail_output_init()
39 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
51 if (gma_power_begin(dev, 0)) { in oaktrail_set_brightness()
69 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
100 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_backlight_init()
106 return 0; in oaktrail_backlight_init()
125 struct psb_pipe *p = &regs->pipe[0]; in oaktrail_save_display_registers()
165 for (i = 0; i < 256; i++) in oaktrail_save_display_registers()
204 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
208 } while (pp_stat & 0x80000000); in oaktrail_save_display_registers()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c20 #define INVALID_REG_ADDR 0xffffffff
23 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
24 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
25 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
26 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
27 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
28 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
29 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
30 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
31 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
22 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
26 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
28 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
30 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7902),
73 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
74 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
75 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
41 d-cache-size = <0x8000>; // L1, 32 KB
42 i-cache-size = <0x8000>; // L1, 32 KB
48 cache-size = <0x40000>; // L2, 256 KB
98 hysteresis = <0>;
104 hysteresis = <0>;
110 hysteresis = <0>;
133 #clock-cells = <0>;
[all …]
/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_defs.h45 #define FE_LED0 (1<<0)
88 #define ISCON 0x10 /* connected to scsi */
89 #define CRST 0x08 /* force reset */
90 #define IARB 0x02 /* immediate arbitration */
93 #define SDU 0x80 /* cmd: disconnect will raise error */
94 #define CHM 0x40 /* sta: chained mode */
95 #define WSS 0x08 /* sta: wide scsi send [W]*/
96 #define WSR 0x01 /* sta: wide scsi received [W]*/
99 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
100 #define ULTRA 0x80 /* cmd: ULTRA enable */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
/linux/drivers/message/fusion/
H A Dmptbase.c83 module_param(mpt_msi_enable_spi, int, 0);
85 " Enable MSI Support for SPI controllers (default=0)");
88 module_param(mpt_msi_enable_fc, int, 0);
90 " Enable MSI Support for FC controllers (default=0)");
93 module_param(mpt_msi_enable_sas, int, 0);
95 " Enable MSI Support for SAS controllers (default=0)");
98 module_param(mpt_channel_mapping, int, 0);
99 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
106 " debug level - refer to mptdebug.h - (default=0)");
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]