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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfaraday,ftpci100.txt9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
H A Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
H A Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
H A Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-goramo-multilink.dts25 memory@0 {
31 reg = <0x00000000 0x4000000>;
53 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
68 flash@0,0 {
74 reg = <0 0x00000000 0x1000000>;
78 /* Eraseblock at 0x0fe000
[all...]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x2000000
[all...]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k2000.dtsi17 #size-cells = <0>;
22 reg = <0x0>;
29 reg = <0x1>;
36 #clock-cells = <0>;
51 thermal-sensors = <&tsensor 0>;
71 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
72 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
73 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
74 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
82 ranges = <1 0x0 0x0 0x18400000 0x4000>;
[all …]
H A Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v3.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0x0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0xc000>;
40 reg = <0x1>;
42 d-cache-size = <0x8000>;
45 i-cache-size = <0xc000>;
54 reg = <0x2>;
56 d-cache-size = <0x8000>;
[all …]
/freebsd/sys/dev/firewire/
H A Dfwohcireg.h38 #define PCI_CBMEM PCIR_BAR(0)
40 #define FW_VENDORID_NATSEMI 0x100B
41 #define FW_VENDORID_NEC 0x1033
42 #define FW_VENDORID_SIS 0x1039
43 #define FW_VENDORID_TI 0x104c
44 #define FW_VENDORID_SONY 0x104d
45 #define FW_VENDORID_VIA 0x1106
46 #define FW_VENDORID_RICOH 0x1180
47 #define FW_VENDORID_APPLE 0x106b
48 #define FW_VENDORID_LUCENT 0x11c1
[all …]
/freebsd/sys/dev/xl/
H A Dif_xlreg.h35 #define XL_EE_READ 0x0080 /* read, 5 bit address */
36 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38 #define XL_EE_EWEN 0x0030 /* erase, no data needed */
39 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40 #define XL_EE_BUSY 0x8000
42 #define XL_EE_EADDR0 0x00 /* station address, first word */
43 #define XL_EE_EADDR1 0x01 /* station address, next word, */
44 #define XL_EE_EADDR2 0x02 /* station address, last word */
45 #define XL_EE_PRODID 0x03 /* product ID code */
[all …]

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