Searched +full:0 +full:x53fb0000 (Results 1 – 7 of 7) sorted by relevance
20 reg = <0x53fb0000 0x4000>;
49 reg = <0x53fb0000 0x4000>;
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;73 #phy-cells = <0>;78 #phy-cells = <0>;92 reg = <0x43f00000 0x100000>;97 reg = <0x43f00000 0x4000>;102 #size-cells = <0>;[all …]
57 #define EPIT_CR 0x00 /* Control register */59 #define EPIT_CR_CLKSRC_OFF 071 #define EPIT_CR_EN (1u << 0)73 #define EPIT_SR 0x04 /* Status register */74 #define EPIT_SR_OCIF (1u << 0)76 #define EPIT_LR 0x08 /* Load register */77 #define EPIT_CMPR 0x0c /* Compare register */78 #define EPIT_CNR 0x10 /* Counter register */90 #define ET_MAX_TICKS 0xfffffffe114 static const uint32_t imx51_epit_ioaddr[2] = {0x73fac000, 0x73fb0000};[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0x0>;52 d-cache-size = <0x8000>;53 i-cache-size = <0x8000>;55 l2-cache-line = <0x40000>;56 timebase-frequency = <0>;57 bus-frequency = <0>;58 clock-frequency = <0>;62 localbus@0fffc000 {[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]