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Searched +full:0 +full:x53000 (Results 1 – 12 of 12) sorted by relevance

/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/drivers/virt/vboxguest/
H A Dvmmdev.h17 #define VMMDEV_PORT_OFF_REQUEST 0
50 #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
72 #define VMMDEV_EVENT_VALID_EVENT_MASK 0x000007ffU
79 #define VMMDEV_VERSION 0x00010004
81 #define VMMDEV_VERSION_MINOR (VMMDEV_VERSION & 0xffff)
87 #define VMMDEV_REQUEST_HEADER_VERSION 0x10001
124 #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
155 #define VMMDEV_MOUSE_RANGE_MIN 0
157 #define VMMDEV_MOUSE_RANGE_MAX 0xFFFF
181 #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_offset.h29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
34 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
35 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
36 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
38 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-sdx75.c67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8917.c58 .offset = 0x21000,
61 .enable_reg = 0x45008,
76 .offset = 0x21000,
79 .enable_reg = 0x45000,
80 .enable_mask = BIT(0),
93 .offset = 0x21000,
106 { 700000000, 1400000000, 0 },
110 { 525000000, 1066000000, 0 },
115 .config_ctl_val = 0x4001055b,
116 .early_output_mask = 0,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]