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Searched +full:0 +full:x53000 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dpq2fads.dts26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x60>;
52 ranges = <0x0 0x0 0xff800000 0x800000
53 0x1 0x0 0xf4500000 0x8000
54 0x8 0x0 0xf8200000 0x8000>;
[all …]
H A Dmpc8272ads.dts25 #size-cells = <0>;
27 PowerPC,8272@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x40>;
52 ranges = <0x0 0x0 0xff800000 0x00800000
53 0x1 0x0 0xf4500000 0x8000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos54xx.dtsi42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sram/
H A Dsram.yaml159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_hsi_debug_tools.h37 GRCBASE_GRC = 0x50000,
38 GRCBASE_MISCS = 0x9000,
39 GRCBASE_MISC = 0x8000,
40 GRCBASE_DBU = 0xa000,
41 GRCBASE_PGLUE_B = 0x2a8000,
42 GRCBASE_CNIG = 0x218000,
43 GRCBASE_CPMU = 0x30000,
44 GRCBASE_NCSI = 0x40000,
45 GRCBASE_OPTE = 0x53000,
46 GRCBASE_BMB = 0x540000,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]