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/linux/drivers/clk/visconti/
H A Dclkc-tmpv770x.c43 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
45 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
47 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
50 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
51 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
52 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
67 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
71 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/linux/drivers/gpib/tnt4882/
H A Dmite.h14 #define PCI_VENDOR_ID_NATINST 0x1093
64 #define CHAN_OFFSET(x) (0x100 * (x))
66 /* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
68 #define MITE_CHOR 0x500
81 #define CHOR_START BIT(0)
84 #define MITE_CHCR 0x504
102 #define CHCR_FIFO_ON 0
104 #define CHCR_NO_BURSTEN 0
106 #define CHCR_NFTP0 CHCR_NFTP(0)
113 #define CHCR_NETP0 CHCR_NETP(0)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
H A Dga102.c37 nvkm_falcon_mask(&gsp->falcon, 0x1668, 0x00000111, 0x00000111); in ga102_gsp_reset()
38 return 0; in ga102_gsp_reset()
66 cnt, hshdr->sig_prod_offset + sig, 0, 0); in ga102_gsp_booter_ctor()
72 fw->imem_base_img = lhdr->app[0].offset; in ga102_gsp_booter_ctor()
73 fw->imem_base = 0; in ga102_gsp_booter_ctor()
74 fw->imem_size = lhdr->app[0].size; in ga102_gsp_booter_ctor()
77 fw->dmem_base = 0; in ga102_gsp_booter_ctor()
81 fw->boot_addr = lhdr->app[0].offset; in ga102_gsp_booter_ctor()
83 fw->fuse_ver = meta[0]; in ga102_gsp_booter_ctor()
101 int idx = 0; in ga102_gsp_fwsec_signature()
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
H A Dbcm6858.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0x0 0x0 0x81000000 0x8000>;
105 reg = <0x1000 0x1000>, /* GICD */
[all …]
H A Dbcm63158.dtsi19 #size-cells = <0>;
21 B53_0: cpu@0 {
24 reg = <0x0 0x0>;
32 reg = <0x0 0x1>;
40 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
81 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
109 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm6846.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
82 ranges = <0 0x81000000 0x8000>;
89 reg = <0x1000 0x1000>,
90 <0x2000 0x2000>,
91 <0x4000 0x2000>,
[all …]
H A Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
H A Dbcm63178.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
100 ranges = <0 0x81000000 0x8000>;
107 reg = <0x1000 0x1000>,
[all …]
H A Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
62 reg = <0xe0110000 0x10000>;
64 #size-cells = <0>;
69 #clock-cells = <0>;
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
73 reg = <0x624 0>;
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi.h17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
[all …]
/linux/Documentation/mm/
H A Dpage_owner.rst81 post_alloc_hook+0x177/0x1a0
82 get_page_from_freelist+0xd01/0xd80
83 __alloc_pages+0x39e/0x7e0
84 allocate_slab+0xbc/0x3f0
85 ___slab_alloc+0x528/0x8a0
86 kmem_cache_alloc+0x224/0x3b0
87 sk_prot_alloc+0x58/0x1a0
88 sk_alloc+0x32/0x4f0
89 inet_create+0x427/0xb50
90 __sock_create+0x2e4/0x650
[all …]
/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c22 #define DDRC_PERF_CTRL 0x010
23 #define DDRC_FLUX_WR 0x380
24 #define DDRC_FLUX_RD 0x384
25 #define DDRC_FLUX_WCMD 0x388
26 #define DDRC_FLUX_RCMD 0x38c
27 #define DDRC_PRE_CMD 0x3c0
28 #define DDRC_ACT_CMD 0x3c4
29 #define DDRC_RNK_CHG 0x3cc
30 #define DDRC_RW_CHG 0x3d0
31 #define DDRC_EVENT_CTRL 0x6C0
[all …]
/linux/drivers/media/pci/saa7134/
H A Dsaa7134-tvaudio.c42 } while (0)
167 #define SAA7134_MUTE_MASK 0xbb
168 #define SAA7134_MUTE_ANALOG 0x04
169 #define SAA7134_MUTE_I2S 0x40
175 int ausel=0, ics=0, ocs=0; in mute_input_7134()
215 case TV: ausel=0xc0; ics=0x00; ocs=0x02; break; in mute_input_7134()
216 case LINE1: ausel=0x80; ics=0x00; ocs=0x00; break; in mute_input_7134()
217 case LINE2: ausel=0x80; ics=0x08; ocs=0x01; break; in mute_input_7134()
218 case LINE2_LEFT: ausel=0x80; ics=0x08; ocs=0x05; break; in mute_input_7134()
220 saa_andorb(SAA7134_AUDIO_FORMAT_CTRL, 0xc0, ausel); in mute_input_7134()
[all …]

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