Home
last modified time | relevance | path

Searched +full:0 +full:x520 (Results 1 – 25 of 117) sorted by relevance

12345

/linux/drivers/clk/hisilicon/
H A Dclk-hi6220.c23 { HI6220_REF32K, "ref32k", NULL, 0, 32764, },
24 { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, },
25 { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, },
26 { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, },
27 { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, },
28 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, },
29 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,},
30 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,},
31 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,},
32 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxpedite5200.dts30 #size-cells = <0>;
32 PowerPC,8548@0 {
34 reg = <0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
45 reg = <0x0 0x0>; // Filled in by U-Boot
52 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
58 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dxpedite5200_xmon.dts18 boot-bank = <0x0>;
34 #size-cells = <0>;
36 PowerPC,8548@0 {
38 reg = <0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
49 reg = <0x0 0x0>; // Filled in by boot loader
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
H A Dstx_gp3_8560.dts27 #size-cells = <0>;
29 PowerPC,8560@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0 0xfdf00000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
H A Dasp834x-redboot.dts25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x8000000>; // 128MB at 0
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
56 0 0 0xf0000000 0x02000000
[all …]
H A Dksi8560.dts33 #size-cells = <0>;
35 PowerPC,8560@0 {
37 reg = <0>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
43 bus-frequency = <0>; /* From U-boot */
44 clock-frequency = <0>; /* From U-boot */
51 reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
58 ranges = <0x00000000 0xfdf00000 0x00100000>;
[all …]
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
H A Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi.h17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dregs.h9 #define MT_MDP_BASE 0x820cd000
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
61 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
63 #define MT_INFRA_CFG_BASE 0xfe000
66 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c)
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c644 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
646 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
653 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31),
655 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7),
656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
657 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23),
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]

12345