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27 #size-cells = <0>;29 cpu0: cpu@0 {32 reg = <0>;36 i-cache-size = <0x8000>;38 d-cache-size = <0x8000>;52 i-cache-size = <0x8000>;54 d-cache-size = <0x8000>;77 reg = <0x80000000 0x400000>, /* sram0 4 MiB */78 <0x80400000 0x200000>, /* sram1 2 MiB */79 <0x80600000 0x200000>; /* aisram 2 MiB */[all …]